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Added provisional coremark files from work with Elizabeth
This commit is contained in:
Teo Ene
parent
07641203ee
commit
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90
wally-pipelined/config/coremark/wally-config.vh
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90
wally-pipelined/config/coremark/wally-config.vh
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@ -0,0 +1,90 @@
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//////////////////////////////////////////
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// wally-config.vh
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//
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// Written: David_Harris@hmc.edu 4 January 2021
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// Modified:
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//
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// Purpose: Specify which features are configured
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// Macros to determine which modes are supported based on MISA
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 64
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//`define MISA (32'h00000104)
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`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12)
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`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
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`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
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`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
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`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
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`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
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`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
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`define ZCSR_SUPPORTED 1
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`define ZCOUNTERS_SUPPORTED 1
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// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
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//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
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`define N_SUPPORTED 0
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`define M_MODE (2'b11)
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`define S_MODE (2'b01)
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`define U_MODE (2'b00)
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// Microarchitectural Features
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`define UARCH_PIPELINED 1
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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`define MEM_DCACHE 0
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`define MEM_DTIM 1
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`define MEM_ICACHE 0
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`define MEM_VIRTMEM 0
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// Address space
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//`define RESET_VECTOR 64'h0000000080000000
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`define RESET_VECTOR 64'h0000000000000000
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// Bus Interface width
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`define AHBW 64
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define TIMBASE 32'h80000000
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`define TIMRANGE 32'h0007FFFF
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`define CLINTBASE 32'h02000000
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`define CLINTRANGE 32'h0000FFFF
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`define GPIOBASE 32'h10012000
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`define GPIORANGE 32'h000000FF
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`define UARTBASE 32'h10000000
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`define UARTRANGE 32'h00000007
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// Test modes
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// Tie GPIO outputs back to inputs
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`define GPIO_LOOPBACK_TEST 0
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// Hardware configuration
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`define UART_PRESCALE 1
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/* verilator lint_off STMTDLY */
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/* verilator lint_off WIDTH */
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/* verilator lint_off ASSIGNDLY */
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/* verilator lint_off PINCONNECTEMPTY */
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@ -7,11 +7,11 @@
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#
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# Takes 1:10 to run RV64IC tests using gui
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# Use this wally-pipelined.do file to run this example.
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# Use this wally-coremark.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do
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# do wally-coremark.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined.do -c
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# vsim -do wally-coremark.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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@ -27,12 +27,9 @@ vlib work
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# default to config/rv64ic, but allow this to be overridden at the command line. For example:
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# do wally-pipelined.do ../config/rv32ic
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switch $argc {
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0 {vlog +incdir+../config/rv64ic ../testbench/testbench-coremark.sv ../src/*/*.sv -suppress 2583}
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1 {vlog +incdir+$1 ../testbench/testbench-coremark.sv ../src/*/*.sv -suppress 2583}
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}
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# default to config/coremark, but allow this to be overridden at the command line. For example:
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vlog +incdir+../config/coremark ../testbench/testbench-coremark.sv ../src/*/*.sv -suppress 2583
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc work.testbench -o workopt
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@ -58,11 +55,14 @@ add wave /testbench/dut/hart/FlushW
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add wave -divider
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add wave -hex /testbench/dut/hart/ifu/PCF
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add wave -hex /testbench/dut/hart/ifu/InstrF
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add wave /testbench/InstrFName
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#add wave -hex /testbench/dut/hart/ifu/PCD
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add wave -hex /testbench/dut/hart/ifu/InstrD
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add wave /testbench/InstrDName
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add wave -divider
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#add wave -hex /testbench/dut/hart/ifu/PCE
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#add wave -hex /testbench/dut/hart/ifu/InstrE
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add wave /testbench/InstrEName
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add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
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add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
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add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
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@ -70,11 +70,13 @@ add wave /testbench/dut/hart/ieu/dp/PCSrcE
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add wave -divider
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#add wave -hex /testbench/dut/hart/ifu/PCM
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#add wave -hex /testbench/dut/hart/ifu/InstrM
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add wave /testbench/InstrMName
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add wave /testbench/dut/uncore/dtim/memwrite
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add wave -hex /testbench/dut/uncore/HADDR
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add wave -hex /testbench/dut/uncore/HWDATA
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add wave -divider
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add wave -hex /testbench/dut/hart/ifu/PCW
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add wave /testbench/InstrWName
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add wave /testbench/dut/hart/ieu/dp/RegWriteW
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add wave -hex /testbench/dut/hart/ieu/dp/ResultW
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add wave -hex /testbench/dut/hart/ieu/dp/RdW
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@ -1,11 +1,40 @@
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///////////////////////////////////////////
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// testbench-imperas.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Wally Testbench and helper modules
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// Applies test programs from the Imperas suite
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module testbench();
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logic clk;
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logic reset;
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string memfilename;
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int test, i, errors, totalerrors;
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logic [31:0] sig32[0:10000];
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logic [`XLEN-1:0] signature[0:10000];
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logic [`XLEN-1:0] testadr;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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logic [`XLEN-1:0] meminit;
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string tests[];
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [31:0] HADDR;
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@ -17,31 +46,167 @@ module testbench();
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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// pick tests based on modes supported
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initial
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tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.memfile", "1000"};
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string signame, memfilename;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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// instantiate device to be tested
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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assign HREADYEXT = 1;
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assign HRESPEXT = 0;
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assign HRDATAEXT = 0;
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wallypipelinedsoc dut(.*);
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wallypipelinedsoc dut(.*);
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// Track names of instructions
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, InstrW,
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InstrDName, InstrEName, InstrMName, InstrWName);
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// initialize tests
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initial
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begin
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memfilename = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.memfile";
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totalerrors = 0;
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// read test vectors into memory
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memfilename = tests[0];
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$readmemh(memfilename, dut.imem.RAM);
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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reset = 1; # 22; reset = 0;
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end
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// generate clock to sequence tests
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always
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begin
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clk = 1; # 5; clk = 0; # 5;
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end
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endmodule
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/* verilator lint_on STMTDLY */
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/* verilator lint_on WIDTH */
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module instrTrackerTB(
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input logic clk, reset, FlushE,
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input logic [31:0] InstrD,
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input logic [31:0] InstrE, InstrM,
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output logic [31:0] InstrW,
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output string InstrDName, InstrEName, InstrMName, InstrWName);
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// stage Instr to Writeback for visualization
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flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
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instrNameDecTB ddec(InstrD, InstrDName);
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instrNameDecTB edec(InstrE, InstrEName);
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instrNameDecTB mdec(InstrM, InstrMName);
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instrNameDecTB wdec(InstrW, InstrWName);
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endmodule
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// decode the instruction name, to help the test bench
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module instrNameDecTB(
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input logic [31:0] instr,
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output string name);
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logic [6:0] op;
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logic [2:0] funct3;
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logic [6:0] funct7;
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logic [11:0] imm;
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assign op = instr[6:0];
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assign funct3 = instr[14:12];
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assign funct7 = instr[31:25];
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assign imm = instr[31:20];
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// it would be nice to add the operands to the name
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// create another variable called decoded
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always_comb
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casez({op, funct3})
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10'b0000000_000: name = "BAD";
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10'b0000011_000: name = "LB";
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10'b0000011_001: name = "LH";
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10'b0000011_010: name = "LW";
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10'b0000011_011: name = "LD";
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10'b0000011_100: name = "LBU";
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10'b0000011_101: name = "LHU";
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10'b0000011_110: name = "LWU";
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10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
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else name = "ADDI";
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10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
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else name = "ILLEGAL";
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10'b0010011_010: name = "SLTI";
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10'b0010011_011: name = "SLTIU";
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10'b0010011_100: name = "XORI";
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10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
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else if (funct7[6:1] == 6'b010000) name = "SRAI";
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else name = "ILLEGAL";
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10'b0010011_110: name = "ORI";
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10'b0010011_111: name = "ANDI";
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10'b0010111_???: name = "AUIPC";
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10'b0100011_000: name = "SB";
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10'b0100011_001: name = "SH";
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10'b0100011_010: name = "SW";
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10'b0100011_011: name = "SD";
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10'b0011011_000: name = "ADDIW";
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10'b0011011_001: name = "SLLIW";
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10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
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else if (funct7 == 7'b0100000) name = "SRAIW";
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else name = "ILLEGAL";
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10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
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else if (funct7 == 7'b0100000) name = "SUBW";
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else if (funct7 == 7'b0000001) name = "MULW";
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else name = "ILLEGAL";
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10'b0111011_001: if (funct7 == 7'b0000000) name = "SLLW";
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else if (funct7 == 7'b0000001) name = "DIVW";
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else name = "ILLEGAL";
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10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
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else if (funct7 == 7'b0100000) name = "SRAW";
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else if (funct7 == 7'b0000001) name = "DIVUW";
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else name = "ILLEGAL";
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10'b0111011_110: if (funct7 == 7'b0000001) name = "REMW";
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else name = "ILLEGAL";
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10'b0111011_111: if (funct7 == 7'b0000001) name = "REMUW";
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else name = "ILLEGAL";
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10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
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else if (funct7 == 7'b0000001) name = "MUL";
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else if (funct7 == 7'b0100000) name = "SUB";
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else name = "ILLEGAL";
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10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
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else if (funct7 == 7'b0000001) name = "MULH";
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else name = "ILLEGAL";
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10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
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else if (funct7 == 7'b0000001) name = "MULHSU";
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else name = "ILLEGAL";
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10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
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else if (funct7 == 7'b0000001) name = "MULHU";
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else name = "ILLEGAL";
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10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
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else if (funct7 == 7'b0000001) name = "DIV";
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else name = "ILLEGAL";
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10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
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else if (funct7 == 7'b0000001) name = "DIVU";
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else if (funct7 == 7'b0100000) name = "SRA";
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else name = "ILLEGAL";
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10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
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else if (funct7 == 7'b0000001) name = "REM";
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else name = "ILLEGAL";
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10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
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else if (funct7 == 7'b0000001) name = "REMU";
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else name = "ILLEGAL";
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10'b0110111_???: name = "LUI";
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10'b1100011_000: name = "BEQ";
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10'b1100011_001: name = "BNE";
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10'b1100011_100: name = "BLT";
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10'b1100011_101: name = "BGE";
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10'b1100011_110: name = "BLTU";
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10'b1100011_111: name = "BGEU";
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10'b1100111_000: name = "JALR";
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10'b1101111_???: name = "JAL";
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10'b1110011_000: if (imm == 0) name = "ECALL";
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else if (imm == 1) name = "EBREAK";
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else if (imm == 2) name = "URET";
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else if (imm == 258) name = "SRET";
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else if (imm == 770) name = "MRET";
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else name = "ILLEGAL";
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10'b1110011_001: name = "CSRRW";
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10'b1110011_010: name = "CSRRS";
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10'b1110011_011: name = "CSRRC";
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10'b1110011_101: name = "CSRRWI";
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10'b1110011_110: name = "CSRRSI";
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10'b1110011_111: name = "CSRRCI";
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10'b0001111_???: name = "FENCE";
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default: name = "ILLEGAL";
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endcase
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endmodule
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