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https://github.com/openhwgroup/cvw
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small busybear testbench changes
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@ -13,7 +13,7 @@ module testbench_busybear();
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logic [31:0] InstrF;
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logic [7:0] ByteMaskM;
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logic InstrAccessFaultF, DataAccessFaultM;
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logic TimerIntM, SwIntM; // from CLINT
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logic TimerIntM = 0, SwIntM = 0; // from CLINT
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logic ExtIntM = 0; // not yet connected
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// for now, seem to need these to be zero until we get a better idea
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@ -50,10 +50,20 @@ module testbench_busybear();
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end
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// read memreads trace file
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integer data_file_mem, scan_file_mem;
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integer data_file_memR, scan_file_memR;
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initial begin
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data_file_mem = $fopen("busybear-testgen/parsedMemRead.txt", "r");
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if (data_file_mem == 0) begin
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data_file_memR = $fopen("busybear-testgen/parsedMemRead.txt", "r");
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if (data_file_memR == 0) begin
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$display("file couldn't be opened");
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$stop;
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end
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end
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// read memwrite trace file
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integer data_file_memW, scan_file_memW;
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initial begin
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data_file_memW = $fopen("busybear-testgen/parsedMemWrite.txt", "r");
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if (data_file_memW == 0) begin
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$display("file couldn't be opened");
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$stop;
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end
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@ -74,6 +84,10 @@ module testbench_busybear();
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for(int j=1; j<32; j++) begin
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// read 31 integer registers
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scan_file_rf = $fscanf(data_file_rf, "%x\n", rfExpected[j]);
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if($feof(data_file_rf)) begin
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$display("no more rf data to read");
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$stop;
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end
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// check things!
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if (rf[j*64+63 -: 64] != rfExpected[j]) begin
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$display("%t ps: rf[%0d] does not equal rf expected: %x, %x", $time, j, rf[j*64+63 -: 64], rfExpected[j]);
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@ -83,9 +97,21 @@ module testbench_busybear();
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end
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// this might need to change
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always @(MemRWM or DataAdrM) begin
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if (MemRWM != 0) begin
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scan_file_mem = $fscanf(data_file_mem, "%x\n", ReadDataM);
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always @(MemRWM[1] or DataAdrM) begin
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if (MemRWM[1]) begin
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scan_file_memR = $fscanf(data_file_memR, "%x\n", ReadDataM);
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end
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end
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logic [`XLEN-1:0] writeDataExpected;
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// this might need to change
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always @(WriteDataM or DataAdrM or ByteMaskM) begin
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if (MemRWM[0]) begin
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$display("!!!!");
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
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if (writeDataExpected != WriteDataM) begin
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$display("%t ps: WriteDataM does not equal WriteDataExpected: %x, %x", $time, WriteDataM, writeDataExpected);
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end
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end
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end
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@ -95,16 +121,26 @@ module testbench_busybear();
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nextSpec = 0;
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end
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integer instrs;
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initial begin
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instrs = 0;
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end
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always @(PCF) begin
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speculative <= nextSpec;
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if (speculative) begin
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speculative <= (PCF != pcExpected);
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nextSpec <= (PCF != pcExpected);
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end
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if (~speculative) begin
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// first read instruction
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scan_file_PC = $fscanf(data_file_PC, "%x\n", InstrF);
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// then expected PC value
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scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
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$display("loaded %0d instructions", instrs);
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instrs += 1;
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if($feof(data_file_PC)) begin
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$display("no more PC data to read");
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$stop;
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end
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// are we at a branch/jump?
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case (InstrF[6:0]) //todo: add C versions of these
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7'b1101111, //JAL
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@ -46,6 +46,10 @@ add wave -hex /testbench_busybear/dut/dp/InstrF
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add wave -divider
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# registers!
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add wave -hex /testbench_busybear/rfExpected
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add wave -hex /testbench_busybear/MemRWM[0]
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add wave -hex /testbench_busybear/MemRWM[1]
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add wave -hex /testbench_busybear/ByteMaskM
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add wave -hex /testbench_busybear/WriteDataM
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add wave -hex /testbench_busybear/dut/dp/regf/rf[1]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[2]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[3]
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@ -87,7 +91,7 @@ add wave -hex /testbench_busybear/dut/dp/PCE
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add wave /testbench_busybear/InstrEName
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#add wave -hex /testbench_busybear/dut/dp/SrcAE
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#add wave -hex /testbench_busybear/dut/dp/SrcBE
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#add wave -hex /testbench_busybear/dut/dp/ALUResultE
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add wave -hex /testbench_busybear/dut/dp/ALUResultE
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#add wave /testbench_busybear/dut/dp/PCSrcE
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#add wave -divider
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add wave -hex /testbench_busybear/dut/dp/PCM
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@ -121,6 +125,6 @@ add wave /testbench_busybear/InstrWName
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#set DefaultRadix hexadecimal
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#
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#-- Run the Simulation
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run 300
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run 700
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#run -all
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##quit
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