mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-30 00:14:28 +00:00
597dd1e7e6
Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler. |
||
---|---|---|
.. | ||
bin | ||
config | ||
regression | ||
src | ||
testbench | ||
testgen | ||
lint-wally |