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Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.

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About 149307ns of simulation run.
This commit is contained in:
Ross Thompson 2021-02-18 21:32:15 -06:00
parent 8cbc9f7e51
commit 7d6093b302
6 changed files with 81 additions and 37 deletions
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45
wally-pipelined/regression/wave.do
View File

@ -4,14 +4,15 @@ add wave -noupdate /testbench/clk
add wave -noupdate /testbench/reset
add wave -noupdate -divider <NULL>
add wave -noupdate /testbench/dut/hart/ebu/IReadF
add wave -noupdate -group HDU /testbench/dut/hart/DataStall
add wave -noupdate -group HDU /testbench/dut/hart/InstrStall
add wave -noupdate -group HDU /testbench/dut/hart/StallF
add wave -noupdate -group HDU /testbench/dut/hart/StallD
add wave -noupdate -group HDU /testbench/dut/hart/FlushD
add wave -noupdate -group HDU /testbench/dut/hart/FlushE
add wave -noupdate -group HDU /testbench/dut/hart/FlushM
add wave -noupdate -group HDU /testbench/dut/hart/FlushW
add wave -noupdate -expand -group HDU /testbench/dut/hart/DataStall
add wave -noupdate -expand -group HDU /testbench/dut/hart/InstrStall
add wave -noupdate -expand -group HDU /testbench/dut/hart/hzu/FlushF
add wave -noupdate -expand -group HDU /testbench/dut/hart/StallF
add wave -noupdate -expand -group HDU /testbench/dut/hart/StallD
add wave -noupdate -expand -group HDU /testbench/dut/hart/FlushD
add wave -noupdate -expand -group HDU /testbench/dut/hart/FlushE
add wave -noupdate -expand -group HDU /testbench/dut/hart/FlushM
add wave -noupdate -expand -group HDU /testbench/dut/hart/FlushW
add wave -noupdate -expand -group Bpred -expand -group direction -divider Update
add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdatePC
add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/DirPredictor/UpdateEN
@ -22,8 +23,32 @@ add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/Instr
add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassD
add wave -noupdate -expand -group InstrClass /testbench/dut/hart/ifu/bpred/InstrClassE
add wave -noupdate /testbench/dut/hart/ifu/bpred/InstrF
add wave -noupdate /testbench/dut/hart/ifu/bpred/BPPredWrongE
add wave -noupdate /testbench/dut/hart/ifu/PCNextF
add wave -noupdate /testbench/dut/hart/ifu/PCF
add wave -noupdate /testbench/dut/hart/ifu/PCPlus2or4F
add wave -noupdate /testbench/dut/hart/ifu/PCNext0F
add wave -noupdate /testbench/dut/hart/ifu/PCNext1F
add wave -noupdate /testbench/dut/hart/ifu/SelBPPredF
add wave -noupdate /testbench/dut/hart/ifu/bpred/BTBValidF
add wave -noupdate /testbench/dut/hart/ifu/bpred/BPPredF
add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/ValidBits
add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/LookUpPCIndexQ
add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePCIndexQ
add wave -noupdate /testbench/dut/hart/ifu/bpred/TargetPredictor/LookUpPC
add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE
add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE
add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionDirWrongE
add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE
add wave -noupdate -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE
add wave -noupdate -expand -group BTB -divider Update
add wave -noupdate -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN
add wave -noupdate -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC
add wave -noupdate -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateTarget
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {72 ns} 0}
WaveRestoreCursors {{Cursor 1} {66 ns} 0}
quietly wave cursor active 1
configure wave -namecolwidth 250
configure wave -valuecolwidth 185
@ -39,4 +64,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {329 ns}
WaveRestoreZoom {21 ns} {105 ns}

45
wally-pipelined/src/ifu/BTBPredictor.sv
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@ -32,19 +32,19 @@ module BTBPredictor
#(parameter int Depth = 10
)
(input logic clk,
input logic reset,
input logic [`XLEN-1:0] LookUpPC,
input logic reset,
input logic [`XLEN-1:0] LookUpPC,
output logic [`XLEN-1:0] TargetPC,
output logic Valid,
output logic Valid,
// update
input logic UpdateEN,
input logic [`XLEN-1:0] UpdatePC,
input logic [`XLEN-1:0] UpdateTarget
input logic UpdateEN,
input logic [`XLEN-1:0] UpdatePC,
input logic [`XLEN-1:0] UpdateTarget
);
localparam TotalDepth = 2 ** Depth;
logic [TotalDepth-1:0] ValidBits;
logic [Depth-1:0] LookUpPCIndex, UpdatePCIndex;
logic [Depth-1:0] LookUpPCIndex, UpdatePCIndex, LookUpPCIndexQ, UpdatePCIndexQ;
// hashing function for indexing the PC
// We have Depth bits to index, but XLEN bits as the input.
@ -53,29 +53,44 @@ module BTBPredictor
assign UpdatePCIndex = {UpdatePC[Depth+1] ^ UpdatePC[1], UpdatePC[Depth:2]};
assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]};
flopenr #(Depth) UpdatePCIndexReg(.clk(clk),
.reset(reset),
.en(1'b1),
.d(UpdatePCIndex),
.q(UpdatePCIndexQ));
// The valid bit must be resetable.
always_ff @ (posedge clk) begin
if (reset) begin
ValidBits <= #1 {TotalDepth{1'b0}};
end else if (UpdateEN) begin
ValidBits[UpdatePCIndex] <= #1 1'b1;
ValidBits[UpdatePCIndexQ] <= #1 1'b1;
end
end
flopenr #(Depth) LookupPCIndexReg(.clk(clk),
.reset(reset),
.en(1'b1),
.d(LookUpPCIndex),
.q(LookUpPCIndexQ));
assign Valid = ValidBits[LookUpPCIndexQ];
// the BTB contains the target address.
// *** future version may contain the instruction class, a tag or partial tag,
// and other indirection branch data.
// Another optimization may be using a PC relative address.
SRAM2P1R1W #(Depth, `XLEN) memory(.clk(clk),
.RA1(LookUpPCIndex),
.RD1(TargetPC),
.REN1(1'b1),
.WA1(UpdatePCIndex),
.WD1(UpdateTarget),
.WEN1(UpdateEN),
.BitWEN1({`XLEN{1'b1}}));
.reset(reset),
.RA1(LookUpPCIndex),
.RD1(TargetPC),
.REN1(1'b1),
.WA1(UpdatePCIndex),
.WD1(UpdateTarget),
.WEN1(UpdateEN),
.BitWEN1({`XLEN{1'b1}}));
endmodule

18
wally-pipelined/src/ifu/SramModel.sv
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@ -40,8 +40,10 @@ module SRAM2P1R1W
parameter int Width = 2
)
(input clk,
(input logic clk,
// *** have to remove reset eventually
input logic reset,
// port 1 is read only
input logic [Depth-1:0] RA1,
output logic [Width-1:0] RD1,
@ -59,39 +61,39 @@ module SRAM2P1R1W
logic WEN1Q;
logic [Width-1:0] WD1Q;
logic [Width-1:0] memory [2**Depth-1:0];
logic [Width-1:0] memory [2**Depth-1:0];
// SRAMs address busses are always registered first.
flopenr #(Depth) RA1Reg(.clk(clk),
.reset(1'b0),
.reset(reset),
.en(REN1),
.d(RA1),
.q(RA1Q));
flopenr #(Depth) WA1Reg(.clk(clk),
.reset(1'b0),
.reset(reset),
.en(REN1),
.d(WA1),
.q(WA1Q));
flopenr #(1) WEN1Reg(.clk(clk),
.reset(1'b0),
.reset(reset),
.en(1'b1),
.d(WEN1),
.q(WEN1Q));
flopenr #(Width) WD1Reg(.clk(clk),
.reset(1'b0),
.reset(reset),
.en(REN1),
.d(WD1),
.q(WD1Q));
// read port
assign RD1 = memory[RA1Q];
genvar index;
genvar index;
// write port
generate

6
wally-pipelined/src/ifu/bpred.sv
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@ -162,13 +162,13 @@ module bpred
// Check the prediction makes execution.
assign TargetWrongE = PCTargetE != PCD;
assign FallThroughWrongE = PCLinkE != PCD;
assign PredictionDirWrongE = BPPredE ^ PCSrcE;
assign PredictionDirWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0];
assign PredictionPCWrongE = PCSrcE ? TargetWrongE : FallThroughWrongE;
assign BPPredWrongE = PredictionPCWrongE | PredictionDirWrongE;
assign BPPredWrongE = (PredictionPCWrongE | PredictionDirWrongE) & (|InstrClassE);
// Update predictors
satCounter2 BPDirUpdate(.BrDir(~PredictionDirWrongE),
satCounter2 BPDirUpdate(.BrDir(PCSrcE),
.OldState(BPPredE),
.NewState(UpdateBPPredE));

2
wally-pipelined/src/ifu/twoBitPredictor.sv
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@ -31,6 +31,7 @@ module twoBitPredictor
#(parameter int Depth = 10
)
(input logic clk,
input logic reset,
input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] Prediction,
// update
@ -52,6 +53,7 @@ module twoBitPredictor
SRAM2P1R1W #(Depth, 2) memory(.clk(clk),
.reset(reset),
.RA1(LookUpPCIndex),
.RD1(PredictionMemory),
.REN1(1'b1),

2
wally-pipelined/testbench/testbench-imperas.sv
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@ -329,7 +329,7 @@ string tests32i[] = {
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
$readmemh(memfilename, dut.imem.RAM);
$readmemh(memfilename, dut.uncore.dtim.RAM);
reset = 1; # 22; reset = 0;
reset = 1; # 42; reset = 0;
end
// generate clock to sequence tests