Multiplier tweaks

This commit is contained in:
David Harris 2021-02-17 16:00:27 -05:00
parent e64e8afb7f
commit e8d3c7d9e7
2 changed files with 11 additions and 8 deletions

View File

@ -1,7 +1,8 @@
# check for warnings in Verilog code
# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv
verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv
#verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv src/*/div/*.sv
# --lint-only just runs lint rather than trying to compile and simulate
# -I points to the include directory where files such as `include wally-config.vh are found

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@ -48,16 +48,18 @@ module muldiv (
mul mul(.*);
if (WIDTH==32) begin
divide4x32 div(.clk(clk), .reset(reset),
/*
if (`XLEN==32) begin
int32div div(.clk(clk), .reset(reset),
.N(SrcAE), .D(SrcBE), .Q(QuotE), .rem0(RemE),
.start(), .div0(), .done(), .divone());
end else begin // WIDTH=64
divide4x64 div(.clk(clk), .reset(reset),
.start(), .div0(), .done(), .divdone());
end else begin // XLEN=64
int64div div(.clk(clk), .reset(reset),
.N(SrcAE), .D(SrcBE), .Q(QuotE), .rem0(RemE),
.start(), .div0(), .done(), .divone());
.start(), .div0(), .done(), .divdone());
end
*/
// Select result
always_comb
case (Funct3E)