Added test configurations

wally-pipelined/config/rv32ic/wally-config.vh

@@ -0,0 +1,67 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 32
+
+`define MISA (32'h00000104)
+`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
+`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
+`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
+`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
+`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
+`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
+`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
+`define ZCSR_SUPPORTED 1
+`define ZCOUNTERS_SUPPORTED 1
+// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
+//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
+`define N_SUPPORTED 0
+
+`define M_MODE (2'b11)
+`define S_MODE (2'b01)
+`define U_MODE (2'b00)
+
+// Microarchitectural Features
+`define UARCH_PIPELINED 1
+`define UARCH_SUPERSCALR 0
+`define UARCH_SINGLECYCLE 0
+`define MEM_DCACHE 0
+`define MEM_DTIM 1
+`define MEM_ICACHE 0
+`define MEM_VIRTMEM 0
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 0
+
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+/* verilator lint_off STMTDLY */
+/* verilator lint_off WIDTH */

wally-pipelined/config/rv64ic/wally-config.vh

@@ -0,0 +1,67 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 64
+
+`define MISA (32'h00000104)
+`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
+`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
+`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
+`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
+`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
+`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
+`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
+`define ZCSR_SUPPORTED 1
+`define ZCOUNTERS_SUPPORTED 1
+// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
+//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
+`define N_SUPPORTED 0
+
+`define M_MODE (2'b11)
+`define S_MODE (2'b01)
+`define U_MODE (2'b00)
+
+// Microarchitectural Features
+`define UARCH_PIPELINED 1
+`define UARCH_SUPERSCALR 0
+`define UARCH_SINGLECYCLE 0
+`define MEM_DCACHE 0
+`define MEM_DTIM 1
+`define MEM_ICACHE 0
+`define MEM_VIRTMEM 0
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 0
+
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+/* verilator lint_off STMTDLY */
+/* verilator lint_off WIDTH */

wally-pipelined/regression/regression-wally.py

@@ -0,0 +1,35 @@
+#!/usr/bin/python3
+##################################
+#
+# regression-wally.py
+# David_Harris@Hmc.edu 25 January 2021
+#
+# Run a regression with multiple configurations and report any errors.
+#
+##################################
+
+# edit this line to add more configurations
+confignames = ["rv32ic", "rv64ic"]
+
+import os
+
+fail = 0
+
+for config in confignames:
+  logname = "wally_"+config+".log"
+  cmd = "vsim -c >" + logname +" <<!\ndo wally-pipelined-batch.do ../config/" + config + "\n!\n"
+  os.system(cmd)
+
+  # check for success.  grep returns 0 if found, 1 if not found
+  cmd = "grep 'All tests ran without failures' " + logname + "> /dev/null"
+  grepval = os.system(cmd)
+  if (grepval):
+    fail = fail + 1
+    print(logname+": failures detected")
+  else:
+    print(logname+": Success")
+
+if (fail):
+  print ("Regression failed with " +str(fail)+ " failed configurations")
+else:
+  print ("SUCCESS! All tests ran without failures")

wally-pipelined/regression/sim-wally-batch

@@ -0,0 +1,3 @@
+vsim -c <<!
+do wally-pipelined-batch.do ../config/rv64ic
+!

wally-pipelined/regression/wally-pipelined-batch.do

@@ -10,9 +10,9 @@
 
 # Use this wally-pipelined.do file to run this example.
 # Either bring up ModelSim and type the following at the "ModelSim>" prompt:
-#     do wally-pipelined.do
+#     do wally-pipelined.do ../config/rv64ic
 # or, to run from a shell, type the following at the shell prompt:
-#     vsim -do wally-pipelined.do -c
+#     vsim -c -do wally-pipelined.do ../config/rv64ic
 # (omit the "-c" to see the GUI while running from the shell)
 
 onbreak {resume}
@@ -27,7 +27,8 @@ vlib work
 # suppress spurious warnngs about 
 # "Extra checking for conflicts with always_comb done at vopt time"
 # because vsim will run vopt
-vlog src/*.sv -suppress 2583
+#vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*.sv -suppress 2583
+vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*.sv -suppress 2583
 
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals

wally-pipelined/regression/wally-pipelined.do

@@ -26,7 +26,7 @@ vlib work
 # suppress spurious warnngs about 
 # "Extra checking for conflicts with always_comb done at vopt time"
 # because vsim will run vopt
-vlog src/*.sv -suppress 2583
+vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*.sv -suppress 2583
 
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals

wally-pipelined/sim-wally-batch

@@ -1 +0,0 @@
-vsim -c -do wally-pipelined-batch.do

wally-pipelined/src/uart.sv

@@ -52,7 +52,7 @@ module uart (
   generate
     if (`XLEN == 64) begin
       always_comb begin
-/*        RdUARTM = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
+        RdUARTM = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
         case (AdrM[2:0])
           3'b000: Din = MaskedWriteDataM[7:0];
           3'b001: Din = MaskedWriteDataM[15:8];
@@ -62,7 +62,7 @@ module uart (
           3'b101: Din = MaskedWriteDataM[47:40];
           3'b110: Din = MaskedWriteDataM[55:48];
           3'b111: Din = MaskedWriteDataM[63:56];
-        endcase */
+        endcase 
       end 
     end else begin // 32-bit
       always_comb begin

wally-pipelined/src/wally-macros.sv

@@ -1,33 +0,0 @@
-// wally-macros.sv
-// David_Harris@hmc.edu 5 January 2021
-
-// Macros to determine which mode is supported based on MISA
-
-`define A_SUPPORTED ((MISA >> 0) % 2 == 1)
-`define C_SUPPORTED ((MISA >> 2) % 2 == 1)
-`define D_SUPPORTED ((MISA >> 3) % 2 == 1)
-`define F_SUPPORTED ((MISA >> 5) % 2 == 1)
-`define M_SUPPORTED ((MISA >> 12) % 2 == 1)
-`define S_SUPPORTED ((MISA >> 18) % 2 == 1)
-`define U_SUPPORTED ((MISA >> 20) % 2 == 1)
-`define ZCSR_SUPPORTED (ZCSR != 0)
-`define ZCOUNTERS_SUPPORTED (ZCOUNTERS != 0)
-// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
-//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
-`define N_SUPPORTED 0
-
-`define M_MODE (2'b11)
-`define S_MODE (2'b01)
-`define U_MODE (2'b00)
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 0
-
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-/* verilator lint_off STMTDLY */
-/* verilator lint_off WIDTH */

wally-pipelined/testbench/testbench-imperas.sv

@@ -1,10 +1,11 @@
 ///////////////////////////////////////////
-// testbench.sv
+// testbench-imperas.sv
 //
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
 // Purpose: Wally Testbench and helper modules
+//          Applies test programs from the Imperas suite
 // 
 // A component of the Wally configurable RISC-V project.
 // 
@@ -265,7 +266,7 @@ string tests32i[] = {
        // dut.dmem.RAM[i] = meminit;
       end
       // read test vectors into memory
-      memfilename = {"../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
+      memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
       $readmemh(memfilename, dut.imem.RAM);
       $readmemh(memfilename, dut.dmem.dtim.RAM);
       reset = 1; # 22; reset = 0;
@@ -290,7 +291,7 @@ string tests32i[] = {
         end
 
         // read signature, reformat in 64 bits if necessary
-        signame = {"../imperas-riscv-tests/work/", tests[test], ".signature.output"};
+        signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"};
         $readmemh(signame, sig32);
         i = 0;
         while (i < 10000) begin
@@ -337,7 +338,7 @@ string tests32i[] = {
           $stop;
         end
         else begin
-          memfilename = {"../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
+          memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
           $readmemh(memfilename, dut.imem.RAM);
           $readmemh(memfilename, dut.dmem.dtim.RAM);
           $display("Read memfile %s", memfilename);