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Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time.

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This commit is contained in:
James E. Stine 2021-04-01 12:30:37 -05:00
parent 6aed8eaea1
commit 59dee5580c
12 changed files with 2168 additions and 0 deletions
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63
wally-pipelined/regression/wally-pipelined-muldiv.do Normal file
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# wally-pipelined.do
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# Use this wally-pipelined.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do wally-pipelined.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do wally-pipelined.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined.do ../config/rv32ic
switch $argc {
0 {vlog +incdir+../config/rv64imc ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt +acc work.testbench -o workopt
vsim workopt
view wave
-- display input and output signals as hexidecimal values
do ./wave-dos/ahb-waves.do
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {100 ps}
configure wave -namecolwidth 250
configure wave -valuecolwidth 140
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
set DefaultRadix hexadecimal
-- Run the Simulation
#run 4100
run -all
#quit

BIN
wally-pipelined/src/muldiv/div/div Executable file
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22
wally-pipelined/src/muldiv/div/div.c Normal file
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#include <stdio.h>
#include <math.h>
#include <inttypes.h>
int main() {
uint64_t N;
uint64_t D;
uint64_t Q;
N = 0xc9649f05a8e1a8bb;
D = 0x82f6747f707af2c0;
Q = N/D;
printf("N = %" PRIx64 "\n", N);
printf("D = %" PRIx64 "\n", D);
printf("Q = %" PRIx64 "\n", Q);
printf("R = %" PRIx64 "\n", N%D);
}

21
wally-pipelined/src/muldiv/div/div.c~ Normal file
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#include <stdio.h>
#include <math.h>
#include <inttypes.h>
int main() {
uint64_t N;
uint64_t D;
uint64_t Q;
N = 0xc9649f05a8e1a8bb;
D = 0x82f6747f707af2c0;
printf("N = %" PRIx64 "\n", N);
printf("D = %" PRIx64 "\n", D);
printf("Q = %" PRIx64 "\n", Q);
printf("R = %" PRIx64 "\n", N%D);
}

107
wally-pipelined/src/muldiv/div/div64.out Normal file
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1535
wally-pipelined/src/muldiv/div/div64_sim/div.sv Executable file
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108
wally-pipelined/src/muldiv/div/div64_sim/flop.sv Normal file
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///////////////////////////////////////////
// flop.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: arious flavors of flip-flops
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
// ordinary flip-flop
module flop #(parameter WIDTH = 8) (
input logic clk,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
q <= #1 d;
endmodule
// flop with asynchronous reset
module flopr #(parameter WIDTH = 8) (
input logic clk, reset,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk, posedge reset)
if (reset) q <= #1 0;
else q <= #1 d;
endmodule
// flop with enable
module flopen #(parameter WIDTH = 8) (
input logic clk, en,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk)
if (en) q <= #1 d;
endmodule
// flop with enable, asynchronous reset, synchronous clear
module flopenrc #(parameter WIDTH = 8) (
input logic clk, reset, clear, en,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk, posedge reset)
if (reset) q <= #1 0;
else if (en)
if (clear) q <= #1 0;
else q <= #1 d;
endmodule
// flop with enable, asynchronous reset
module flopenr #(parameter WIDTH = 8) (
input logic clk, reset, en,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk, posedge reset)
if (reset) q <= #1 0;
else if (en) q <= #1 d;
endmodule
// flop with enable, asynchronous load
module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
input logic clk, load, en,
input TYPE d,
input TYPE val,
output TYPE q);
always_ff @(posedge clk, posedge load)
if (load) q <= #1 val;
else if (en) q <= #1 d;
endmodule
// flop with asynchronous reset, synchronous clear
module floprc #(parameter WIDTH = 8) (
input logic clk,
input logic reset,
input logic clear,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
always_ff @(posedge clk, posedge reset)
if (reset) q <= #1 0;
else
if (clear) q <= #1 0;
else q <= #1 d;
endmodule

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wally-pipelined/src/muldiv/div/div64_sim/iter32.do Executable file
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# Copyright 1991-2007 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog div.sv test_iter32.sv
# start and run simulation
vsim -voptargs=+acc work.tb
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 9586700ns
quit

50
wally-pipelined/src/muldiv/div/div64_sim/iter64.do Executable file
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# Copyright 1991-2007 Mentor Graphics Corporation
#
# Modification by Oklahoma State University
# Use with Testbench
# James Stine, 2008
# Go Cowboys!!!!!!
#
# All Rights Reserved.
#
# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# Use this run.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do run.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do run.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
vlog mux.sv flop.sv div.sv test_iter64.sv
# start and run simulation
vsim -voptargs=+acc work.tb
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {75 ns}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
-- Run the Simulation
run 9586700ns
quit

66
wally-pipelined/src/muldiv/div/div64_sim/mux.sv Normal file
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///////////////////////////////////////////
// mux.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: Various flavors of multiplexers
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
module mux2 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule
module mux3 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, d2,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? d2 : (s[0] ? d1 : d0);
endmodule
module mux4 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, d2, d3,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
endmodule
module mux5 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, d2, d3, d4,
input logic [2:0] s,
output logic [WIDTH-1:0] y);
assign y = s[2] ? d4 : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
endmodule
module mux6 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5,
input logic [2:0] s,
output logic [WIDTH-1:0] y);
assign y = s[2] ? (s[0] ? d5 : d4) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
endmodule
/* verilator lint_on DECLFILENAME */

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wally-pipelined/src/muldiv/div/div64_sim/test_iter32.sv Executable file
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@ -0,0 +1,74 @@
module tb;
logic [31:0] N, D;
logic clk;
logic reset;
logic start;
logic [31:0] Q;
logic [31:0] rem0;
logic div0;
logic done;
logic divdone;
integer handle3;
integer desc3;
integer i;
bit [31:0] Ncomp;
bit [31:0] Dcomp;
bit [31:0] Qcomp;
bit [31:0] Rcomp;
logic [7:0] count [0:15];
int32div dut (Q, done, divdone, rem0, div0, N, D, clk, reset, start);
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial
begin
handle3 = $fopen("iter32.out");
#8000000 $finish;
end
always @(posedge clk, posedge reset)
begin
desc3 = handle3;
#0 start = 1'b0;
#0 reset = 1'b1;
#30 reset = 1'b0;
for (i=0; i<2; i=i+1)
begin
N = $random;
D = $random;
start <= 1'b1;
// Wait 2 cycles (to be sure)
repeat (2)
@(posedge clk);
start <= 1'b0;
repeat (25)
@(posedge clk);
Ncomp = N;
Dcomp = D;
Qcomp = Ncomp/Dcomp;
Rcomp = Ncomp%Dcomp;
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
N, D, Q, rem0, Qcomp, Rcomp,
(Q==Qcomp), (rem0==Rcomp));
end // for (i=0; i<2, i=i+1)
end
endmodule // tb

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wally-pipelined/src/muldiv/div/div64_sim/test_iter64.sv Executable file
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module tb;
logic [63:0] N, D;
logic clk;
logic reset;
logic start;
logic [63:0] Q;
logic [63:0] rem0;
logic div0;
logic done;
logic divdone;
integer handle3;
integer desc3;
integer i;
bit [63:0] Ncomp;
bit [63:0] Dcomp;
bit [63:0] Qcomp;
bit [63:0] Rcomp;
logic [7:0] count [0:15];
div dut (Q, done, divdone, rem0, div0, N, D, clk, reset, start);
initial
begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial
begin
handle3 = $fopen("iter64.out");
#8000000 $finish;
end
always @(posedge clk, posedge reset)
begin
desc3 = handle3;
#0 start = 1'b0;
#0 reset = 1'b1;
#30 reset = 1'b0;
for (i=0; i<2; i=i+1)
begin
N = $random;
D = $random;
start <= 1'b1;
// Wait 2 cycles (to be sure)
repeat (2)
@(posedge clk);
start <= 1'b0;
repeat (41)
@(posedge clk);
Ncomp = N;
Dcomp = D;
Qcomp = Ncomp/Dcomp;
Rcomp = Ncomp%Dcomp;
$fdisplay(desc3, "%h %h %h %h || %h %h || %b %b",
N, D, Q, rem0, Qcomp, Rcomp,
(Q==Qcomp), (rem0==Rcomp));
end // for (i=0; i<2, i=i+1)
end
endmodule // tb