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https://github.com/openhwgroup/cvw
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JALR testing
This commit is contained in:
bbracker
parent
5de23fcbe0
commit
7852d866ef
@ -162,6 +162,7 @@ string tests64iNOc[] = {
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"rv64i/WALLY-SRAI", "3000",
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"rv64i/WALLY-LOAD", "11bf0",
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"rv64i/WALLY-JAL", "4000",
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"rv64i/WALLY-JALR", "3000",
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"rv64i/WALLY-STORE", "3000",
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"rv64i/WALLY-ADDIW", "3000",
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"rv64i/WALLY-SLLIW", "3000",
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@ -288,6 +289,7 @@ string tests32i[] = {
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"rv32i/WALLY-SUB", "3000",
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"rv32i/WALLY-STORE", "2000",
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"rv32i/WALLY-JAL", "3000",
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"rv32i/WALLY-JALR", "2000",
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"rv32i/WALLY-BEQ" ,"4000",
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"rv32i/WALLY-BNE", "4000 ",
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"rv32i/WALLY-BLTU", "4000 ",
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@ -19,9 +19,8 @@ from random import getrandbits
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from copy import deepcopy
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##################################
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# functions
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# helper functions
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##################################
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def InitTestGroup():
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global TestGroup,TestGroupSizes,AllRegs,UnusedRegs,StoreAdrReg
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TestGroup += 1
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@ -44,19 +43,21 @@ def registerSelect():
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if len(UnusedRegs)==0:
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InitTestGroup()
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rd = choice(UnusedRegs)
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rs = choice(UnusedRegs)
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UnusedRegs.remove(rd)
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OtherRegs = deepcopy(UnusedRegs)
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if 0 in OtherRegs:
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OtherRegs.remove(0)
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if len(OtherRegs) == 0:
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OtherRegs = deepcopy(AllRegs)
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OtherRegs.remove(0)
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rs = choice(OtherRegs)
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OtherRegs = deepcopy(AllRegs)
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OtherRegs.remove(StoreAdrReg)
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OtherRegs.remove(rd)
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try:
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if 0 in OtherRegs:
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OtherRegs.remove(0)
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except:
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pass
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try:
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if rs in OtherRegs:
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OtherRegs.remove(rs)
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except:
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pass
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DataReg = choice(OtherRegs)
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OtherRegs.remove(DataReg)
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OtherRd = choice(OtherRegs)
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@ -65,52 +66,74 @@ def registerSelect():
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def addInst(line):
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global CurrAdr
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f.write(line)
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if ("li x" in line):
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if ("li x" in line) and ("slli x" not in line):
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CurrAdr += 8 if (xlen == 32) else 20
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elif ("la x" in line):
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CurrAdr += 8
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else:
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CurrAdr += 4
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def writeForwardsJumpVector(spacers):
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global TestNum
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rd, rs, DataReg, OtherRd = registerSelect()
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if (xlen==64):
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expected = int("fedbca9876540000",16)
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unexpected = int("ffff0000ffff0000",16)
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def expectValue(expectReg, expectVal, sigOffset):
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global TestGroupSizes
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TestGroupSizes[TestGroup-1] += 1
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addInst(" "+storecmd+" x"+str(expectReg)+", "+str(wordsize*sigOffset)+"(x"+str(StoreAdrReg)+")\n")
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f.write(" RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(expectReg)+", "+formatstr.format(expectVal)+")\n")
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if (xlen == 32):
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r.write(formatrefstr.format(expectVal)+"\n")
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else:
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expected = int("fedbca98",16)
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unexpected = int("ff00ff00",16)
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r.write(formatrefstr.format(expectVal % 2**32)+"\n" + formatrefstr.format(expectVal >> 32)+"\n")
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def addJalr(rs,rd,dist):
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target = CurrAdr + 20 + dist
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target31_12 = CurrAdr >> 12 # 20 bits for lui
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target11_0 = target - (target31_12 << 12) # 12 remaining bits
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target31_16 = target31_12 >> 4 # lui sign extends, so shift in a leading 0
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target15_12 = target31_12 - (target31_16 << 4) # the nibble we just lost
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if target11_0 > 0:
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offset = randint(-(1<<11)-1,(1<<11)-2-target11_0)
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else:
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offset = randint(-(1<<11)-1-target11_0,(1<<11)-2)
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addInst(" lui x"+str(rs)+", 0x"+imm20formatstr.format(target31_16)+"\n")
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addInst(" addi x"+str(rs)+", x"+str(rs)+", SEXT_IMM(0x0"+imm12formatstr.format(target15_12 << 8)+")\n")
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addInst(" slli x"+str(rs)+", x"+str(rs)+", SEXT_IMM(4)\n")
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addInst(" addi x"+str(rs)+", x"+str(rs)+", SEXT_IMM(0x"+imm12formatstr.format(0xfff&(offset+target11_0+randint(0,1)))+")\n")
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addInst(" JALR x"+str(rd)+", x"+str(rs)+", SEXT_IMM(0x"+imm12formatstr.format(0xfff&(-offset))+")\n")
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##################################
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# test functions
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##################################
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def writeForwardsJumpVector(spacers,instr):
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global TestNum
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TestNum += 1
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rd, rs, DataReg, OtherRd = registerSelect()
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# Header
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f.write("\n")
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f.write(" # Testcase "+str(TestNum)+" address cmp result rd:x"+str(rd)+"("+formatstr.format(CurrAdr+44)+") data result rd:x"+str(DataReg)+"("+formatstr.format(expected)+")\n")
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f.write(" # Testcase "+str(TestNum)+"\n")
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# Test Code
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addInst(" li x"+str(DataReg)+", "+formatstr.format(expected)+"\n")
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addInst(" JAL x"+str(rd)+", 1f\n")
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if (instr=="JAL"):
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addInst(" JAL x"+str(rd)+", 1f\n")
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elif (instr=="JALR"):
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dist = spacers*(8 if (xlen == 32) else 20) # Compute distance from linked adr to target adr
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addJalr(rs,rd,dist);
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else:
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exit("invalid instruction")
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LinkAdr = CurrAdr if (rd!=0) else 0 # rd's expected value
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for i in range(spacers):
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addInst(" li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n")
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f.write("1:\n")
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addInst(" "+storecmd+" x"+str(rd)+", "+str(wordsize*(2*TestNum+0))+"(x"+str(StoreAdrReg)+")\n")
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f.write(" RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(rd)+", "+formatstr.format(LinkAdr)+")\n")
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addInst(" "+storecmd+" x"+str(DataReg)+", "+str(wordsize*(2*TestNum+1))+"(x"+str(StoreAdrReg)+")\n")
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f.write(" RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(DataReg)+", "+formatstr.format(expected)+")\n")
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writeExpectedToRef(LinkAdr)
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writeExpectedToRef(expected)
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TestNum = TestNum+1
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# Store values to be verified
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expectValue(rd, LinkAdr, 2*TestNum+0)
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expectValue(DataReg, expected, 2*TestNum+1)
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def writeBackwardsJumpVector(spacers):
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def writeBackwardsJumpVector(spacers,instr):
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global TestNum
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rd, rs, DataReg,OtherRd = registerSelect()
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if (xlen==64):
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expected = int("fedbca9876540000",16)
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unexpected = int("ffff0000ffff0000",16)
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else:
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expected = int("fedbca98",16)
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unexpected = int("ff00ff00",16)
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TestNum += 1
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rd, rs, DataReg, OtherRd = registerSelect()
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# Header
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f.write("\n")
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f.write(" # Testcase "+str(TestNum)+" address cmp result rd:x"+str(rd)+"("+formatstr.format(CurrAdr+20+8*spacers)+") data result rd:x"+str(DataReg)+"("+formatstr.format(expected)+")\n")
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f.write(" # Testcase "+str(TestNum)+"\n")
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# Test Code
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addInst(" JAL x"+str(OtherRd)+", 2f\n")
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f.write("1:\n")
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addInst(" li x"+str(DataReg)+", "+formatstr.format(expected)+"\n")
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@ -118,29 +141,27 @@ def writeBackwardsJumpVector(spacers):
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f.write("2:\n")
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for i in range(spacers):
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addInst(" li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n")
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addInst(" JAL x"+str(rd)+", 1b\n")
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if (instr=="JAL"):
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addInst(" JAL x"+str(rd)+", 1b\n")
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elif (instr=="JALR"):
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dist = -20 - 4 - (1+spacers)*(8 if (xlen == 32) else 20) # Compute distance from linked adr to target adr
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addJalr(rs,rd,dist);
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else:
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exit("invalid instruction")
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LinkAdr = CurrAdr if (rd!=0) else 0 # rd's expected value
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f.write("3:\n")
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addInst(" "+storecmd+" x"+str(rd)+", "+str(wordsize*(2*TestNum+0))+"(x"+str(StoreAdrReg)+")\n")
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f.write(" RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(rd)+", "+formatstr.format(LinkAdr)+")\n")
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addInst(" "+storecmd+" x"+str(DataReg)+", "+str(wordsize*(2*TestNum+1))+"(x"+str(StoreAdrReg)+")\n")
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f.write(" RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(DataReg)+", "+formatstr.format(expected)+")\n")
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writeExpectedToRef(LinkAdr)
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writeExpectedToRef(expected)
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TestNum = TestNum+1
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# Store values to be verified
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expectValue(rd, LinkAdr, 2*TestNum+0)
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expectValue(DataReg, expected, 2*TestNum+1)
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def writeChainVector(repetitions,spacers):
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global TestNum
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TestNum += 1
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rd, rs, DataReg,OtherRd = registerSelect()
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if (xlen==64):
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expected = int("fedbca9876540000",16)
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unexpected = int("ffff0000ffff0000",16)
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else:
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expected = int("fedbca98",16)
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unexpected = int("ff00ff00",16)
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# Header
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f.write("\n")
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f.write(" # Testcase "+str(TestNum)+" address cmp result rd:x"+str(rd)+"(ugh; if you really wanted to, you could figure it out) data result rd:x"+str(DataReg)+"("+formatstr.format(expected)+")\n")
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f.write(" # Testcase "+str(TestNum)+"\n")
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# Test Code
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addInst(" li x"+str(DataReg)+", "+formatstr.format(expected)+"\n")
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for i in range(repetitions):
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addInst(" JAL x"+str(OtherRd)+", "+str(3*i+2)+"f\n")
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@ -159,57 +180,56 @@ def writeChainVector(repetitions,spacers):
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for j in range(i):
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addInst(" li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n")
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f.write(str(3*i+3)+":\n")
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addInst(" "+storecmd+" x"+str(rd)+", "+str(wordsize*(2*TestNum+0))+"(x"+str(StoreAdrReg)+")\n")
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f.write(" RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(rd)+", "+formatstr.format(LinkAdr)+")\n")
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addInst(" "+storecmd+" x"+str(DataReg)+", "+str(wordsize*(2*TestNum+1))+"(x"+str(StoreAdrReg)+")\n")
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f.write(" RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(DataReg)+", "+formatstr.format(expected)+")\n")
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writeExpectedToRef(LinkAdr)
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writeExpectedToRef(expected)
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TestNum = TestNum+1
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def writeExpectedToRef(expected):
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global TestGroupSizes
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TestGroupSizes[TestGroup-1] += 1
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if (xlen == 32):
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r.write(formatrefstr.format(expected)+"\n")
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else:
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r.write(formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32)+"\n")
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# Store values to be verified
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expectValue(rd, LinkAdr, 2*TestNum+0)
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expectValue(DataReg, expected, 2*TestNum+1)
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##################################
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# main body
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##################################
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# change these to suite your tests
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tests = ["JAL"]
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test = 0
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tests = ["JAL","JALR"]
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author = "Ben Bracker (bbracker@hmc.edu)"
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xlens = [32,64]
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numtests = 100;
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numtests = 100
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# setup
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seed(0) # make tests reproducible
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# generate files for each test
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for xlen in xlens:
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CurrAdr = int("80000108",16)
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TestNum = 0
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TestGroup = 1
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TestGroupSizes = [0]
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AllRegs = list(range(0,32))
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UnusedRegs = deepcopy(AllRegs)
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StoreAdrReg = 6 # matches what's in header script
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UnusedRegs.remove(6)
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for test in tests:
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for xlen in xlens:
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print(test+" "+str(xlen))
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CurrAdr = int("80000108",16)
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TestNum = -1
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TestGroup = 1
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TestGroupSizes = [0]
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AllRegs = list(range(0,32))
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UnusedRegs = deepcopy(AllRegs)
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StoreAdrReg = 6 # matches what's in header script
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UnusedRegs.remove(6)
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if (xlen==64):
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expected = int("fedbca9876540000",16)
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unexpected = int("ffff0000ffff0000",16)
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else:
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expected = int("fedbca98",16)
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unexpected = int("ff00ff00",16)
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formatstrlen = str(int(xlen/4))
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formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
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formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
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imm20formatstr = "{:05x}"
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imm12formatstr = "{:03x}"
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if (xlen == 32):
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storecmd = "sw"
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wordsize = 4
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else:
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storecmd = "sd"
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wordsize = 8
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formatstrlen = str(int(xlen/4))
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formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
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formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
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if (xlen == 32):
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storecmd = "sw"
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wordsize = 4
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else:
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storecmd = "sd"
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wordsize = 8
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for test in tests:
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imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
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basename = "WALLY-" + test
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fname = imperaspath + "src/" + basename + ".S"
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@ -221,7 +241,7 @@ for xlen in xlens:
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f.write("///////////////////////////////////////////\n")
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f.write("// "+fname+ "\n")
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f.write("//\n")
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f.write("// This file can be used to test the RISC-V JAL instruction.\n")
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f.write("// This file can be used to test the RISC-V JAL(R) instruction.\n")
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f.write("// But be warned that altering the test environment may break this test!\n")
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f.write("// In order to work, this test expects that the first instruction (la)\n")
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f.write("// be allocated at 0x80000100.\n")
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@ -235,14 +255,24 @@ for xlen in xlens:
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f.write(line)
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# print directed test vectors
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for i in range(0,31):
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writeForwardsJumpVector(randint(0,4))
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for i in range(0,31):
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writeBackwardsJumpVector(randint(0,4))
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writeForwardsJumpVector(100)
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writeBackwardsJumpVector(100)
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writeChainVector(6,True)
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writeChainVector(16,False)
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if test == "JAL":
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for i in range(0,31):
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writeForwardsJumpVector(randint(0,4),"JAL")
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for i in range(0,31):
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writeBackwardsJumpVector(randint(0,4),"JAL")
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writeForwardsJumpVector(100,"JAL")
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writeBackwardsJumpVector(100,"JAL")
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writeChainVector(6,True)
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writeChainVector(16,False)
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elif test == "JALR":
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for i in range(0,31):
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writeForwardsJumpVector(randint(0,4),"JALR")
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for i in range(0,31):
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writeBackwardsJumpVector(randint(0,4),"JALR")
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# can't make these latter two too long else 12 bit immediate overflows
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# (would need to lui or slli rs to achieve longer ranges)
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writeForwardsJumpVector(15,"JALR")
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writeBackwardsJumpVector(15,"JALR")
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# print footer
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h = open("testgen_footer.S", "r")
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@ -254,7 +284,3 @@ for xlen in xlens:
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f.write("\nRV_COMPLIANCE_DATA_END\n")
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f.close()
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r.close()
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