mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
major progress.
It's running the icache is imperas tests now. Compressed does not work yet.
This commit is contained in:
Ross Thompson
parent
a861a37b72
commit
269ea7997c
@ -162,55 +162,55 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
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add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
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add wave -noupdate -expand -group parameters /testbench/dut/hart/ifu/icache/controller/AHBByteLength
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add wave -noupdate -expand -group parameters /testbench/dut/hart/ifu/icache/controller/AHBOFFETWIDTH
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add wave -noupdate -expand -group parameters /testbench/dut/hart/ifu/icache/controller/BlockByteLength
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add wave -noupdate -expand -group parameters /testbench/dut/hart/ifu/icache/controller/OFFSETWIDTH
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add wave -noupdate -expand -group parameters /testbench/dut/hart/ifu/icache/controller/WORDSPERLINE
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add wave -noupdate -expand -group parameters /testbench/dut/hart/ifu/icache/controller/LOGWPL
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add wave -noupdate -expand -group parameters /testbench/dut/hart/ifu/icache/controller/LINESIZE
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
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add wave -noupdate -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
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add wave -noupdate -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
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add wave -noupdate -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
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add wave -noupdate -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWritePAdr
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add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
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add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBByteLength
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add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBOFFETWIDTH
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add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/BlockByteLength
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add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/OFFSETWIDTH
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add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/WORDSPERLINE
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add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LOGWPL
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add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LINESIZE
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
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add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWritePAdr
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add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
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add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid
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add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadTag
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add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag
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add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadAddr
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add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
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add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadPAdr
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add wave -noupdate -expand -group icache -group memory -expand -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
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add wave -noupdate -expand -group icache -group memory -expand -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
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add wave -noupdate -expand -group icache -group memory -expand -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WritePAdr
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add wave -noupdate -expand -group icache -group memory -expand -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteSet
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add wave -noupdate -expand -group icache -group memory -expand -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteTag
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add wave -noupdate -expand -group icache -group memory -expand -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD
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add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/InstrRawD
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPF
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
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add wave -noupdate -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD
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add wave -noupdate -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/InstrRawD
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCMux
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPFinalF
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/DataValid
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/ReadTag
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/DataTag
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/WriteLine
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/WritePAdr
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/WriteSet
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/WriteTag
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadAddr
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/ReadPAdr
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add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/ICacheMemReadData
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/genblk2/PCPreFinalF_q
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate /testbench/dut/hart/ifu/icache/controller/SavePC
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 2} {44 ns} 0} {{Cursor 2} {566 ns} 0}
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WaveRestoreCursors {{Cursor 2} {44 ns} 0} {{Cursor 2} {1598 ns} 0}
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 229
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@ -226,4 +226,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {458 ns} {674 ns}
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WaveRestoreZoom {1559 ns} {1783 ns}
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@ -206,14 +206,14 @@ module icachecontroller #(parameter LINESIZE = 256) (
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assign PCNextPF = {UpperPCNextPF, LowerPCNextF};
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flopenl #(`XLEN) PCPFFlop(clk, reset, SavePC, PCPFinalF, `RESET_VECTOR, PCPF);
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flopenl #(`XLEN) PCPFFlop(clk, reset, SavePC & ~StallF, PCPFinalF, `RESET_VECTOR, PCPF);
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// on spill we want to get the first 2 bytes of the next cache block.
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// the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can
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// simply add 2 to land on the next cache block.
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assign PCSpillF = PCPF + 2'b10;
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// now we have to select between these three PCs
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assign PCPreFinalF = PCMux[0] ? PCPF : PCNextPF;
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assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextPF; // *** don't like the stallf
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assign PCPFinalF = PCMux[1] ? PCSpillF : PCPreFinalF;
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@ -568,15 +568,19 @@ module icachecontroller #(parameter LINESIZE = 256) (
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generate
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if( `XLEN == 32) begin
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logic [1:1] PCPreFinalF_q;
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flop #(1) PCFReg(.clk(clk),
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.d(PCPreFinalF[1]),
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.q(PCPreFinalF_q[1]));
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flopenr #(1) PCFReg(.clk(clk),
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.reset(reset),
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.en(~StallF),
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.d(PCPreFinalF[1]),
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.q(PCPreFinalF_q[1]));
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assign FinalInstrRawF = PCPreFinalF_q[1] ? {SpillDataBlock0, ICacheMemReadData[31:16]} : ICacheMemReadData;
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end else begin
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logic [2:1] PCPreFinalF_q;
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flop #(2) PCFReg(.clk(clk),
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.d(PCPreFinalF[2:1]),
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.q(PCPreFinalF_q[2:1]));
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flopenr #(2) PCFReg(.clk(clk),
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.reset(reset),
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.en(~StallF),
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.d(PCPreFinalF[2:1]),
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.q(PCPreFinalF_q[2:1]));
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mux4 #(32) AlignmentMux(.d0(ICacheMemReadData[31:0]),
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.d1(ICacheMemReadData[47:16]),
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.d2(ICacheMemReadData[63:32]),
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