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	Switched coremark to RV64IM
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				@ -111,6 +111,6 @@ set DefaultRadix hexadecimal
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-- Run the Simulation 
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#run 7402000
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#run 12750
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#run -all
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run 5000
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run -all
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#run 21400
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#quit
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@ -48,7 +48,7 @@ module testbench();
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  // pick tests based on modes supported
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  initial 
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  tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.memfile", "1000"};
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  tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.memfile", "1000"};
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  string signame, memfilename;
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  logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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  logic UARTSin, UARTSout;
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@ -76,8 +76,8 @@ module testbench();
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      $readmemh(memfilename, dut.uncore.dtim.RAM);
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      for(j=268437829; j < 268566528; j = j+1)
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        dut.uncore.dtim.RAM[j] = 64'b0;
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//      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr";
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//      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab";
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//      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";
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//      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab";
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      reset = 1; # 22; reset = 0;
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    end
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  // generate clock to sequence tests
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