Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-23 13:04:28 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fixed mem write checking

Browse Source 
now passes around 50 instructions!
This commit is contained in:
Noah Boorstin 2021-01-25 20:06:13 -05:00
parent 05d4f2d33d
commit 09c92a6b5d
2 changed files with 9 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
wally-pipelined/regression/wally-busybear.do
View File

@ -53,6 +53,7 @@ add wave -hex /testbench_busybear/MemRWM[0]
add wave -hex /testbench_busybear/MemRWM[1]
add wave -hex /testbench_busybear/ByteMaskM
add wave -hex /testbench_busybear/WriteDataM
add wave -hex /testbench_busybear/DataAdrM
add wave -hex /testbench_busybear/dut/dp/regf/rf[1]
add wave -hex /testbench_busybear/dut/dp/regf/rf[2]
add wave -hex /testbench_busybear/dut/dp/regf/rf[3]
@ -128,6 +129,6 @@ add wave /testbench_busybear/InstrWName
#set DefaultRadix hexadecimal
#
#-- Run the Simulation
run 700
run 800
#run -all
##quit

10
wally-pipelined/testbench/testbench-busybear.sv
View File

@ -103,14 +103,18 @@ module testbench_busybear();
end
end
logic [`XLEN-1:0] writeDataExpected;
logic [`XLEN-1:0] writeDataExpected, writeAdrExpected;
// this might need to change
always @(WriteDataM or DataAdrM or ByteMaskM) begin
#1;
if (MemRWM[0]) begin
$display("!!!!");
scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
if (writeDataExpected != WriteDataM) begin
$display("%t ps: WriteDataM does not equal WriteDataExpected: %x, %x", $time, WriteDataM, writeDataExpected);
$display("%t ps: WriteDataM does not equal writeDataExpected: %x, %x", $time, WriteDataM, writeDataExpected);
end
if (writeAdrExpected != DataAdrM) begin
$display("%t ps: DataAdrM does not equal writeAdrExpected: %x, %x", $time, DataAdrM, writeAdrExpected);
end
end
end