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Implemented adrdec for uncore
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@ -57,7 +57,20 @@
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// Address space
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`define RESET_VECTOR 32'h80000000
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// Bus Interface
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define TIMBASE 64'h0000000080000000
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`define TIMRANGE 64'h000000000007FFFF
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`define CLINTBASE 64'h0000000002000000
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`define CLINTRANGE 64'h000000000000FFFF
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`define GPIOBASE 64'h0000000010012000
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`define GPIORANGE 64'h00000000000000FF
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`define UARTBASE 64'h0000000010000000
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`define UARTRANGE 64'h0000000000000007
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// Bus Interface width
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`define AHBW 32
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// Test modes
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@ -58,10 +58,21 @@
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// Address space
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`define RESET_VECTOR 64'h0000000080000000
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// Bus Interface
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// Bus Interface width
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`define AHBW 64
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define TIMBASE 64'h0000000080000000
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`define TIMRANGE 64'h000000000007FFFF
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`define CLINTBASE 64'h0000000002000000
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`define CLINTRANGE 64'h000000000000FFFF
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`define GPIOBASE 64'h0000000010012000
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`define GPIORANGE 64'h00000000000000FF
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`define UARTBASE 64'h0000000010000000
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`define UARTRANGE 64'h0000000000000007
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// Test modes
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44
wally-pipelined/src/adrdec.sv
Normal file
44
wally-pipelined/src/adrdec.sv
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@ -0,0 +1,44 @@
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///////////////////////////////////////////
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// adrdec.sv
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//
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// Written: David_Harris@hmc.edu 29 January 2021
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// Modified:
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//
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// Purpose: Address decoder
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module adrdec (
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input logic [`XLEN-1:0] AdrM,
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input logic [`XLEN-1:0] Base, Range,
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output logic En
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);
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logic [`XLEN-1:0] match;
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// determine if an address is in a range starting at the base
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// for example, if Base = 0x04002000 and range = 0x00000FFF,
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// then anything address between 0x04002000 and 0x04002FFF should match (En=1)
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assign match = (AdrM ~^ Base) | Range;
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assign En = &match;
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endmodule
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@ -52,7 +52,12 @@ module uncore (
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logic UARTIntr;// *** will need to tie INTR to an interrupt handler
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// Address decoding
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// *** generalize, use configurable
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adrdec timdec(AdrM, `TIMBASE, `TIMRANGE, TimEnM);
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adrdec clintdec(AdrM, `CLINTBASE, `CLINTRANGE, CLINTEnM);
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adrdec gpiodec(AdrM, `GPIOBASE, `GPIORANGE, GPIOEnM);
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adrdec uartdec(AdrM, `UARTBASE, `UARTRANGE, UARTEnM);
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/*// *** generalize, use configurable
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generate
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if (`XLEN == 64)
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assign TimEnM = ~(|AdrM[`XLEN-1:32]) & AdrM[31] & ~(|AdrM[30:19]); // 0x000...80000000 - 0x000...8007FFFF
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@ -62,6 +67,7 @@ module uncore (
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assign CLINTEnM = ~(|AdrM[`XLEN-1:26]) & AdrM[25] & ~(|AdrM[24:16]); // 0x02000000-0x0200FFFF
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assign GPIOEnM = (AdrM[31:8] == 24'h10012); // 0x10012000-0x100120FF
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assign UARTEnM = ~(|AdrM[`XLEN-1:29]) & AdrM[28] & ~(|AdrM[27:3]); // 0x10000000-0x10000007
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*/
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// Enable read or write based on decoded address.
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assign MemRWdtimM = MemRWM & {2{TimEnM}};
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