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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Domenico Ottolia 2021-03-16 23:27:09 -04:00
commit 150faf8dd8
2 changed files with 11 additions and 1 deletions
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1
wally-pipelined/config/busybear/wally-config.vh
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@ -38,6 +38,7 @@
`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
`define ZCSR_SUPPORTED 1
`define ZCOUNTERS_SUPPORTED 1
`define COUNTERS 31
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0

11
wally-pipelined/testbench/testbench-busybear.sv
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@ -106,6 +106,7 @@ module testbench_busybear();
end
integer warningCount = 0;
integer instrs;
//logic[63:0] adrTranslation[4:0];
//string translationType[4:0] = {"rf", "writeAdr", "PCW", "PC", "readAdr"};
@ -249,6 +250,15 @@ module testbench_busybear();
end
end
always @(dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW) begin
if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 5 && instrs != 0) begin
$display("!!!!!!illegal (physical) memory access !!!!!!!!!!");
$display("(as a reminder, MCAUSE and MEPC are set by this)");
$display("at %0t ps, instr %0d, HADDR %x", $time, instrs, HADDR);
`ERROR
end
end
`define CHECK_CSR2(CSR, PATH) \
string CSR; \
logic [63:0] expected``CSR``; \
@ -340,7 +350,6 @@ module testbench_busybear();
end
string PCtext, PCtext2;
integer instrs;
initial begin
instrs = 0;
end