mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 10:15:19 +00:00
Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file
This commit is contained in:
Domenico Ottolia
parent
d5f86fadac
commit
fed42ffe19
@ -344,8 +344,7 @@ module testbench();
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string tests64p[] = '{
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"rv64p/WALLY-MCAUSE", "2000",
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"rv64p/WALLY-SCAUSE", "2000",
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"rv64p/WALLY-UCAUSE", "2000",
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"rv64p/WALLY-MEPC", "4000",
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"rv64p/WALLY-MEPC", "5000",
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"rv64p/WALLY-SEPC", "4000",
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"rv64p/WALLY-TVAL", "3000",
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"rv64p/WALLY-MARCHID", "4000",
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@ -357,8 +356,7 @@ module testbench();
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string tests32p[] = '{
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"rv32p/WALLY-MCAUSE", "2000",
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"rv32p/WALLY-SCAUSE", "2000",
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"rv32p/WALLY-UCAUSE", "2000",
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"rv32p/WALLY-MEPC", "4000",
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"rv32p/WALLY-MEPC", "5000",
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"rv32p/WALLY-SEPC", "4000",
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"rv32p/WALLY-TVAL", "3000",
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"rv32p/WALLY-MARCHID", "4000",
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@ -19,4 +19,18 @@ To compile tests without running them in OVPsim, provide -c as the second argume
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```bash
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sh run.sh NAME -c
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```
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The test generator also has a really nice feature that grabs the location of begin_signature after compiling the tests. For example, running `sh run.sh EPC` will output something like this at the end:
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```verilog
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rv64p = '{
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'rv64p/WALLY-MEPC', '5000',
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'rv64p/WALLY-SEPC', '4000'
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};
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rv32p = '{
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'rv32p/WALLY-MEPC', '5000',
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'rv32p/WALLY-SEPC', '4000'
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};
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```
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@ -1,3 +1,5 @@
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#!/bin/bash
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#
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# Written 1 Mar 2021 by Domenico Ottolia (dottolia@hmc.edu)
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#
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@ -25,6 +27,9 @@ then
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then
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cd ~/riscv-wally/imperas-riscv-tests
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make privileged
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exe2memfile.pl work/*/*.elf
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extractFunctionRadix.sh work/rv64p/*.elf.objdump
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fi
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fi
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@ -48,4 +53,22 @@ then
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fi
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cd ~/riscv-wally/wally-pipelined
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printf "\n\n\n#####\nDone!\n#####\n\n"
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printf "\n\n\n#####\nDone!\n#####\n\n"
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cd ~/riscv-wally/imperas-riscv-tests/work
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for isa in "rv64p" "rv32p"; do
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printf "$isa = '{"
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COMMA=""
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for file in "$isa"/*.elf.objdump; do
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if [[ "$file" == *"$1"* ]]; then
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RES=$(grep "^\s*0*8000.000 <begin_signature>" $file)
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RES=$(echo "$RES" | sed -r 's/^0*80+([0-9]+).+?$/\1/g')
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file=$(echo "$file" | sed -r 's/^(.+?)\.elf\.objdump/\1/g')
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printf "$COMMA\n '$file', '${RES}'"
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COMMA=","
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fi
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done
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printf "\n};\n\n"
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done
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cd ~/riscv-wally/wally-pipelined
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@ -30,7 +30,7 @@ def randRegs():
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else:
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return str(reg1), str(reg2), str(reg3)
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def writeVectors(storecmd):
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def writeVectors(storecmd, returningInstruction):
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global testnum
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# Page 6 of unpriviledged spec
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@ -136,9 +136,10 @@ def writeVectors(storecmd):
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""", False, 2)
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# Breakpoint
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writeTest(storecmd, f, r, f"""
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ebreak
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""", False, 3)
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if returningInstruction != "ebreak":
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writeTest(storecmd, f, r, f"""
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ebreak
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""", False, 3)
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# Load Address Misaligned
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writeTest(storecmd, f, r, f"""
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@ -156,22 +157,23 @@ def writeVectors(storecmd):
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# writeTest(storecmd, f, r, f"""
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# ecall
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# """, False, 8, "u")
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if testMode == "u":
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 8, "u")
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if returningInstruction != "ecall":
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if fromMode == "u":
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 8, "u")
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# Environment call from s-mode
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if testMode == "s":
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 9, "s")
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# Environment call from s-mode
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if fromMode == "s":
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 9, "s")
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# Environment call from m-mode
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if testMode == "m":
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 11, "m")
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# Environment call from m-mode
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if fromMode == "m":
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 11, "m")
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# Instruction page fault: 12
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# Load page fault: 13
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@ -209,7 +211,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, mode = "m", resetHander = "
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trapEnd = f"""j _jend{testnum}"""
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lines = f"""
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li x25, 0x7BAD
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li x25, 0xDEADBEA7
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{test}
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_jend{testnum}:
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@ -232,7 +234,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, mode = "m", resetHander = "
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# change these to suite your tests
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author = "dottolia@hmc.edu"
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xlens = [32, 64]
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numrand = 8;
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numrand = 4;
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# setup
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seed(0xC365DDEB9173AB42) # make tests reproducible
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@ -249,12 +251,8 @@ for xlen in xlens:
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storecmd = "sd"
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wordsize = 8
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corners = [
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0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1,
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2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1
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]
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for testMode in ["m", "s"]:
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for testMode in ["m", "s", "u"]:
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imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
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basename = "WALLY-" + testMode.upper() + "CAUSE"
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fname = imperaspath + "src/" + basename + ".S"
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@ -276,64 +274,142 @@ for xlen in xlens:
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for line in h:
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f.write(line)
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lines = f"""
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csrr x31, mtvec
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li x30, 0
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for returningInstruction in ["ebreak", "ecall"]:
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la x1, _j_m_trap
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csrw mtvec, x1
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la x1, _j_s_trap
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csrw stvec, x1
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j _j_t_begin
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# All registers used:
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# x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
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# ...
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# x26: expected epc value
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# x25: value to write to memory
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# ...
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# x19: mtvec old value
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# x18: medeleg old value
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# x17: sedeleg old value
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_j_m_trap:
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csrrs x25, mcause, x0
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csrrs x1, mepc, x0
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addi x1, x1, 4
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csrrw x0, mepc, x1
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bnez x30, _j_all_end
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mret
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_j_s_trap:
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csrrs x25, scause, x0
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csrrs x1, sepc, x0
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addi x1, x1, 4
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csrrw x0, sepc, x1
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sret
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lines = f"""
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add x7, x6, x0
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csrr x19, mtvec
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_j_t_begin:
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"""
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if testMode == "s" or testMode == "u":
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lines += f"""
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li x1, 0b110000000000
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csrrc x28, mstatus, x1
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li x1, 0b{"01" if testMode == "s" else "00"}00000000000
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csrrs x28, mstatus, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the mret instruction
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csrw mepc, x1
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mret
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# We're now in {testMode} mode...
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"""
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f.write(lines)
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if testMode == "u":
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lines += f"""
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csrr x17, sedeleg
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li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"}
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csrs sedeleg, x9
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"""
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lines += f"""
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li x30, 0
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la x1, _j_m_trap_{returningInstruction}
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csrw mtvec, x1
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la x1, _j_s_trap_{returningInstruction}
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csrw stvec, x1
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la x1, _j_u_trap_{returningInstruction}
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csrw utvec, x1
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j _j_t_begin_{returningInstruction}
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_j_m_trap_{returningInstruction}:
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csrrs x1, mepc, x0
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{"csrr x25, mcause" if testMode == "m" else "li x25, 0xBAD00003"}
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addi x1, x1, 4
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csrrw x0, mepc, x1
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bnez x30, _j_all_end_{returningInstruction}
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mret
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_j_s_trap_{returningInstruction}:
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csrrs x1, sepc, x0
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{"csrr x25, scause" if testMode == "s" else "li x25, 0xBAD00001"}
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addi x1, x1, 4
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csrrw x0, sepc, x1
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bnez x30, _j_goto_machine_mode_{returningInstruction}
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sret
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_j_u_trap_{returningInstruction}:
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csrrs x1, uepc, x0
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{"csrr x25, ucause" if testMode == "u" else "li x25, 0xBAD00000"}
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addi x1, x1, 4
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csrrw x0, uepc, x1
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bnez x30, _j_goto_supervisor_mode_{returningInstruction}
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uret
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_j_goto_supervisor_mode_{returningInstruction}:
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j _j_goto_machine_mode_{returningInstruction}
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_j_goto_machine_mode_{returningInstruction}:
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li x30, 1
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{returningInstruction}
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_j_t_begin_{returningInstruction}:
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"""
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fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
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medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111"
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lines += f"""
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csrr x18, medeleg
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li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"}
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csrw medeleg, x9
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"""
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f.write(lines)
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for fromMode in fromModeOptions:
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lines = ""
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if fromMode == "s" or fromMode == "u":
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lines += f"""
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li x1, 0b110000000000
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csrrc x28, mstatus, x1
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li x1, 0b0100000000000
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csrrs x28, mstatus, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the mret instruction
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csrw mepc, x1
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mret
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# We're now in supervisor mode...
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"""
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if fromMode == "u":
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lines += f"""
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li x1, 0b110000000000
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csrrc x28, sstatus, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the sret instruction
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csrw sepc, x1
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sret
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# We're now in user mode...
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"""
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# print directed and random test vectors
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f.write(lines)
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for i in range(0,numrand):
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writeVectors(storecmd, returningInstruction)
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# print directed and random test vectors
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for i in range(0,numrand):
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writeVectors(storecmd)
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f.write(f"""
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li x30, 1
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{returningInstruction}
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_j_all_end_{returningInstruction}:
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csrw mtvec, x19
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csrw medeleg, x18
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""")
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f.write(f"""
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li x30, 1
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ecall
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_j_all_end:
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csrw mtvec, x31
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""")
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# if we're in supervisor mode, this leaves the ebreak instruction untested (we need a way to)
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# get back to machine mode.
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# print footer
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h = open("../testgen_footer.S", "r")
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@ -349,4 +425,3 @@ for xlen in xlens:
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@ -200,25 +200,27 @@ for xlen in xlens:
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_j_t_begin:
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"""
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fromModeOptions = ["s", "u"] if testMode == "m" else ["u"]
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fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
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f.write(lines)
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for fromMode in fromModeOptions:
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lines = ""
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lines += f"""
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li x1, 0b110000000000
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csrrc x28, mstatus, x1
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li x1, 0b0100000000000
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csrrs x28, mstatus, x1
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if fromMode == "s" or fromMode == "u":
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lines += f"""
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li x1, 0b110000000000
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csrrc x28, mstatus, x1
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li x1, 0b0100000000000
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csrrs x28, mstatus, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the mret instruction
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csrw mepc, x1
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mret
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the mret instruction
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csrw mepc, x1
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mret
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# We're now in supervisor mode...
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"""
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# We're now in supervisor mode...
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"""
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if fromMode == "u":
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lines += f"""
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