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Temporarily reverted my last few commits

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This commit is contained in:
Teo Ene 2021-03-17 15:16:01 -05:00
parent e6661ea26a
commit 29634f1475
2 changed files with 3 additions and 10 deletions
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2
wally-pipelined/regression/wally-pipelined.do
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@ -30,7 +30,7 @@ vlib work
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined.do ../config/rv32ic
switch $argc {
0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation

11
wally-pipelined/testbench/testbench-coremark_bare.sv
View File

@ -34,7 +34,6 @@ module testbench();
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
logic [`XLEN-1:0] meminit;
string tests[];
string ProgramAddrMapFile, ProgramLabelMapFile;
logic [`AHBW-1:0] HRDATAEXT;
logic HREADYEXT, HRESPEXT;
logic [31:0] HADDR;
@ -77,8 +76,8 @@ module testbench();
$readmemh(memfilename, dut.uncore.dtim.RAM);
for(j=2371; j < 65535; j = j+1)
dut.uncore.dtim.RAM[j] = 64'b0;
ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr";
ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab";
// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr";
// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab";
reset = 1; # 22; reset = 0;
end
// generate clock to sequence tests
@ -95,12 +94,6 @@ module testbench();
end
end
if (1 == 1) begin : functionRadix
function_radix function_radix(.reset(reset),
.ProgramAddrMapFile(ProgramAddrMapFile),
.ProgramLabelMapFile(ProgramLabelMapFile));
end
initial begin
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.DirPredictor.memory.memory);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);