mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
Thomas Fleming
commit
ac89947e98
3
wally-pipelined/regression/vish_stacktrace.vstf
Normal file
3
wally-pipelined/regression/vish_stacktrace.vstf
Normal file
@ -0,0 +1,3 @@
|
||||
# transcript error: error writing "stdout": broken pipe
|
||||
while executing
|
||||
"puts -nonewline stdout $s"
|
||||
@ -42,7 +42,7 @@ vsim workopt
|
||||
view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
do ./wave-dos/ahb-waves.do
|
||||
do ./wave-dos/ahb-muldiv.do
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
|
||||
96
wally-pipelined/regression/wave-dos/ahb-muldiv.do
Normal file
96
wally-pipelined/regression/wave-dos/ahb-muldiv.do
Normal file
@ -0,0 +1,96 @@
|
||||
add wave /testbench/clk
|
||||
add wave /testbench/reset
|
||||
add wave -divider
|
||||
|
||||
#add wave /testbench/dut/hart/ebu/IReadF
|
||||
add wave -noupdate -divider -height 32 "Stalls"
|
||||
add wave /testbench/dut/hart/DataStall
|
||||
add wave /testbench/dut/hart/InstrStall
|
||||
add wave /testbench/dut/hart/StallF
|
||||
add wave /testbench/dut/hart/StallD
|
||||
add wave /testbench/dut/hart/StallE
|
||||
add wave /testbench/dut/hart/StallM
|
||||
add wave /testbench/dut/hart/StallW
|
||||
add wave /testbench/dut/hart/FlushD
|
||||
add wave /testbench/dut/hart/FlushE
|
||||
add wave /testbench/dut/hart/FlushM
|
||||
add wave /testbench/dut/hart/FlushW
|
||||
|
||||
add wave -noupdate -divider -height 32 "MulDiv"
|
||||
add wave -hex /testbench/dut/hart/mdu/*
|
||||
|
||||
add wave -noupdate -divider -height 32 "Integer Divider"
|
||||
add wave -hex /testbench/dut/hart/mdu/genblk1/div/fsm1/CURRENT_STATE
|
||||
add wave -hex /testbench/dut/hart/mdu/genblk1/div/fsm1/NEXT_STATE
|
||||
add wave -hex /testbench/dut/hart/mdu/genblk1/div/*
|
||||
|
||||
|
||||
|
||||
add wave -noupdate -divider -height 32 "RF"
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/*
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf
|
||||
|
||||
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/hart/ifu/PCF
|
||||
add wave -hex /testbench/dut/hart/ifu/PCD
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrD
|
||||
|
||||
add wave /testbench/InstrDName
|
||||
add wave -hex /testbench/dut/hart/ifu/ic/InstrRawD
|
||||
add wave -hex /testbench/dut/hart/ifu/ic/AlignedInstrD
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/hart/ifu/ic/InstrPAdrF
|
||||
add wave /testbench/dut/hart/ifu/ic/DelayF
|
||||
add wave /testbench/dut/hart/ifu/ic/DelaySideF
|
||||
add wave /testbench/dut/hart/ifu/ic/DelayD
|
||||
add wave -hex /testbench/dut/hart/ifu/ic/MisalignedHalfInstrD
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/hart/ifu/PCE
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrE
|
||||
add wave /testbench/InstrEName
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
|
||||
#add wave /testbench/dut/hart/ieu/dp/PCSrcE
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/hart/ifu/PCM
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrM
|
||||
add wave /testbench/InstrMName
|
||||
add wave /testbench/dut/uncore/dtim/memwrite
|
||||
add wave -hex /testbench/dut/uncore/HADDR
|
||||
add wave -hex /testbench/dut/uncore/HWDATA
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/hart/ebu/MemReadM
|
||||
add wave -hex /testbench/dut/hart/ebu/InstrReadF
|
||||
add wave -hex /testbench/dut/hart/ebu/BusState
|
||||
add wave -hex /testbench/dut/hart/ebu/NextBusState
|
||||
add wave -hex /testbench/dut/hart/ebu/HADDR
|
||||
add wave -hex /testbench/dut/hart/ebu/HREADY
|
||||
add wave -hex /testbench/dut/hart/ebu/HTRANS
|
||||
add wave -hex /testbench/dut/hart/ebu/HRDATA
|
||||
add wave -hex /testbench/dut/hart/ebu/HWRITE
|
||||
add wave -hex /testbench/dut/hart/ebu/HWDATA
|
||||
add wave -hex /testbench/dut/hart/ebu/CaptureDataM
|
||||
add wave -hex /testbench/dut/hart/ebu/InstrStall
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/uncore/dtim/*
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/hart/ifu/PCW
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrW
|
||||
add wave /testbench/InstrWName
|
||||
add wave /testbench/dut/hart/ieu/dp/RegWriteW
|
||||
add wave -hex /testbench/dut/hart/ebu/ReadDataW
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/ResultW
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/RdW
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/uncore/dtim/*
|
||||
add wave -divider
|
||||
|
||||
add wave -hex -r /testbench/*
|
||||
@ -1,75 +0,0 @@
|
||||
# wally-pipelined.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# Use this wally-pipelined.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-pipelined.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined.do ../config/rv32ic
|
||||
switch $argc {
|
||||
0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
|
||||
1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
|
||||
}
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt +acc work.testbench -o workopt
|
||||
vsim workopt
|
||||
|
||||
view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
add wave /testbench/clk
|
||||
add wave /testbench/reset
|
||||
add wave -noupdate -divider -height 32 "Datapath"
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/*
|
||||
add wave -noupdate -divider -height 32 "RF"
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/*
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf
|
||||
add wave -noupdate -divider -height 32 "Control"
|
||||
add wave -hex /testbench/dut/hart/ieu/c/*
|
||||
add wave -noupdate -divider -height 32 "Multiply/Divide"
|
||||
add wave -hex /testbench/dut/hart/mdu/*
|
||||
|
||||
-- Set Wave Output Items
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {100 ps}
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 120
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
set DefaultRadix hexadecimal
|
||||
|
||||
-- Run the Simulation
|
||||
#run 1000
|
||||
run -all
|
||||
#quit
|
||||
@ -8,33 +8,42 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/functionRadix/fun
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
|
||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/InstrStall
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DataStall
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/InstrStall
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DataStall
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
||||
add wave -noupdate /testbench/dut/hart/hzu/StallFCause_Q
|
||||
add wave -noupdate /testbench/dut/hart/hzu/StallDCause_Q
|
||||
add wave -noupdate /testbench/dut/hart/hzu/StallECause_Q
|
||||
add wave -noupdate /testbench/dut/hart/hzu/StallMCause_Q
|
||||
add wave -noupdate /testbench/dut/hart/hzu/StallWCause_Q
|
||||
add wave -noupdate -group Bpred -expand -group direction -divider Update
|
||||
add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/UpdatePC
|
||||
add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/UpdateEN
|
||||
@ -53,7 +62,6 @@ add wave -noupdate -group Bpred -group BTB -divider Lookup
|
||||
add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/TargetPC
|
||||
add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/Valid
|
||||
add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/BPPredWrongE
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrF
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
|
||||
@ -82,7 +90,6 @@ add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
|
||||
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/PCLinkW
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
|
||||
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
|
||||
@ -141,8 +148,32 @@ add wave -noupdate -group {function radix debug} /testbench/functionRadix/functi
|
||||
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionAddr
|
||||
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramAddrIndex
|
||||
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionName
|
||||
add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/InstrD
|
||||
add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/SrcAE
|
||||
add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/SrcBE
|
||||
add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/Funct3E
|
||||
add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/MulDivE
|
||||
add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/W64E
|
||||
add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/StallM
|
||||
add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/StallW
|
||||
add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/FlushM
|
||||
add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/FlushW
|
||||
add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/MulDivResultW
|
||||
add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/genblk1/div/start
|
||||
add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/DivDoneE
|
||||
add wave -noupdate -expand -group muldiv /testbench/dut/hart/mdu/DivBusyE
|
||||
add wave -noupdate /testbench/dut/hart/mdu/genblk1/gclk
|
||||
add wave -noupdate -expand -group divider /testbench/dut/hart/mdu/genblk1/div/fsm1/CURRENT_STATE
|
||||
add wave -noupdate -expand -group divider /testbench/dut/hart/mdu/genblk1/div/N
|
||||
add wave -noupdate -expand -group divider /testbench/dut/hart/mdu/genblk1/div/D
|
||||
add wave -noupdate -expand -group divider /testbench/dut/hart/mdu/genblk1/div/Q
|
||||
add wave -noupdate -expand -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
|
||||
add wave -noupdate /testbench/dut/hart/MulDivResultW
|
||||
add wave -noupdate /testbench/dut/hart/mdu/genblk1/PrelimResultE
|
||||
add wave -noupdate /testbench/dut/hart/mdu/Funct3E
|
||||
add wave -noupdate /testbench/dut/hart/mdu/genblk1/QuotE
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {3758805 ns} 0}
|
||||
WaveRestoreCursors {{Cursor 2} {128433 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 229
|
||||
@ -158,4 +189,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {1644110 ns} {15262484 ns}
|
||||
WaveRestoreZoom {128007 ns} {128663 ns}
|
||||
|
||||
@ -64,35 +64,35 @@ module align(zman, ae, aligncnt, xzero, yzero, zzero, zdenorm, proddenorm, t, bs
|
||||
ps = 0;
|
||||
|
||||
// And to using product as primary operand in adder I exponent gen
|
||||
killprod = 0;
|
||||
killprod = xzero | yzero;
|
||||
// d = aligncnt
|
||||
// p = 53
|
||||
if ($signed(aligncnt) <= $signed(-105)) begin //d<=-2p+1
|
||||
if ($signed(aligncnt) <= $signed(-103)) begin //d<=-2p+1
|
||||
//product ancored case with saturated shift
|
||||
sumshift = 163; // 3p+4
|
||||
sumshiftzero = 0;
|
||||
shift = {~zdenorm,zman,163'b0} >> sumshift;
|
||||
t = {shift[215:52]};
|
||||
t = zzero ? 0 : {shift[215:52]};
|
||||
bs = |(shift[51:0]);
|
||||
//zexpsel = 0;
|
||||
end else if($signed(aligncnt) <= $signed(0)) begin // -2p+1<d<=2
|
||||
end else if($signed(aligncnt) <= $signed(1)) begin // -2p+1<d<=2
|
||||
// set d<=2 to d<=0
|
||||
// product ancored or cancellation
|
||||
// warning: set to 55 rather then 56. was there a typo in the book?
|
||||
sumshift = 55-aligncnt; // p + 3 - d
|
||||
sumshift = 57-aligncnt; // p + 3 - d
|
||||
sumshiftzero = 0;
|
||||
shift = {~zdenorm,zman,163'b0} >> sumshift;
|
||||
t = {shift[215:52]};
|
||||
t = zzero ? 0 : {shift[215:52]};
|
||||
bs = |(shift[51:0]);
|
||||
//zexpsel = 0;
|
||||
end else if ($signed(aligncnt)<=$signed(52)) begin // 2 < d <= p+2
|
||||
end else if ($signed(aligncnt)<=$signed(55)) begin // 2 < d <= p+2
|
||||
// another typo in book? above was 55 changed to 52
|
||||
// addend ancored case
|
||||
// used to be 56 \/ somthing doesn't seem right too many typos
|
||||
sumshift = 55-aligncnt;
|
||||
sumshift = 57-aligncnt;
|
||||
sumshiftzero = 0;
|
||||
shift = {~zdenorm,zman, 163'b0} >> sumshift;
|
||||
t = {shift[215:52]};
|
||||
t = zzero ? 0 : {shift[215:52]};
|
||||
bs = |(shift[51:0]);
|
||||
//zexpsel = 1;
|
||||
end else begin // d >= p+3
|
||||
@ -100,7 +100,7 @@ module align(zman, ae, aligncnt, xzero, yzero, zzero, zdenorm, proddenorm, t, bs
|
||||
sumshift = 0;
|
||||
sumshiftzero = 1;
|
||||
shift = {~zdenorm,zman, 163'b0} >> sumshift;
|
||||
t = {shift[215:52]};
|
||||
t = zzero ? 0 : {shift[215:52]};
|
||||
bs = |(shift[51:0]);
|
||||
killprod = 1;
|
||||
//ps = 1;
|
||||
|
||||
@ -84,8 +84,10 @@ module expgen(xexp, yexp, zexp,
|
||||
// This should not increas the critical path because the time to
|
||||
// check if a round overflows is shorter than the actual round and
|
||||
// is masked by the bypass mux and two 10 bit adder delays.
|
||||
|
||||
assign aligncnt = zexp -ae - 1 + ~xdenorm + ~ydenorm - ~zdenorm;
|
||||
assign aligncnt0 = - 1 + ~xdenorm + ~ydenorm - ~zdenorm;
|
||||
assign aligncnt1 = - 1 + {12'b0,~xdenorm} + {12'b0,~ydenorm} - {12'b0,~zdenorm};
|
||||
assign aligncnt = zexp -ae - 1 + {12'b0,~xdenorm} + {12'b0,~ydenorm} - {12'b0,~zdenorm};
|
||||
//assign aligncnt = zexp -ae - 1 + ~xdenorm + ~ydenorm - ~zdenorm;
|
||||
//assign aligncnt = zexp - ae;// KEP use all of ae
|
||||
|
||||
// Select exponent (usually from product except in case of huge addend)
|
||||
@ -107,7 +109,7 @@ module expgen(xexp, yexp, zexp,
|
||||
// check for exponent out of bounds after add
|
||||
|
||||
assign de = resultdenorm | sumzero ? 0 : de0;
|
||||
assign sumof = de[12];
|
||||
assign sumof = ~de[12] && de > 2046;
|
||||
assign sumuf = de == 0 && ~sumzero && ~resultdenorm;
|
||||
|
||||
// bypass occurs before rounding or taking early results
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
module flag(xnan, ynan, znan, xinf, yinf, zinf, prodof, sumof, sumuf,
|
||||
psign, zsign, xzero, yzero, vbits,
|
||||
psign, zsign, xzero, yzero, zzero, vbits, killprod,
|
||||
inf, nan, invalid, overflow, underflow, inexact);
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
@ -26,6 +26,8 @@ module flag(xnan, ynan, znan, xinf, yinf, zinf, prodof, sumof, sumuf,
|
||||
input zsign; // Sign of z
|
||||
input xzero; // x = 0
|
||||
input yzero; // y = 0
|
||||
input zzero; // y = 0
|
||||
input killprod;
|
||||
input [1:0] vbits; // R and S bits of result
|
||||
output inf; // Some source is Inf
|
||||
output nan; // Some source is NaN
|
||||
@ -73,8 +75,7 @@ module flag(xnan, ynan, znan, xinf, yinf, zinf, prodof, sumof, sumuf,
|
||||
// 1) Any input is denormalized
|
||||
// 2) Output would be denormalized or smaller
|
||||
|
||||
assign underflow = (sumuf && ~inf && ~prodinf && ~nan);
|
||||
|
||||
assign underflow = (sumuf && ~inf && ~prodinf && ~nan) || (killprod & zzero & ~(yzero | xzero));
|
||||
|
||||
// Set the inexact flag for the following cases:
|
||||
// 1) Multiplication inexact
|
||||
|
||||
@ -47,7 +47,7 @@ module normalize(sum, zexp, invz, normcnt, ae, aligncnt, sumshift, sumshiftzero,
|
||||
logic [9:0] sumshifttmp;
|
||||
logic [163:0] sumshiftedtmp; // shifted sum
|
||||
logic sticky;
|
||||
logic tmp,tmp1,tmp2,tmp3;
|
||||
logic tmp,tmp1,tmp2,tmp3,tmp4, tmp5;
|
||||
|
||||
// When the sum is zero, normalization does not apply and only the
|
||||
// sticky bit must be computed. Otherwise, the sum is right-shifted
|
||||
@ -68,16 +68,16 @@ logic tmp,tmp1,tmp2,tmp3;
|
||||
// p = 53
|
||||
// ea + eb = ae
|
||||
// set d<=2 to d<=0
|
||||
if ($signed(aligncnt)<=$signed(0)) begin //d<=2
|
||||
if ($signed(aligncnt)<=$signed(1)) begin //d<=2
|
||||
// product anchored or cancellation
|
||||
if ($signed(ae-normcnt+2) >= $signed(-1022)) begin //ea+eb-l+2 >= emin
|
||||
//normal result
|
||||
sumshifted = sum << (55+normcnt); // p+2+l
|
||||
de0 = xzero|yzero ? zexp : ae-normcnt+2+xdenorm+ydenorm;
|
||||
resultdenorm = |sum & ~|de0;
|
||||
sumshifted = resultdenorm ? sum << sumshift : sum << (55+normcnt); // p+2+l
|
||||
v = sumshifted[162:109];
|
||||
sticky = (|sumshifted[108:0]) | bs;
|
||||
resultdenorm = 0;
|
||||
//de0 = ae-normcnt+2-1023;
|
||||
de0 = xzero|yzero ? zexp : ae-normcnt+2+xdenorm+ydenorm;
|
||||
end else begin
|
||||
sumshifted = sum << (1080+ae);
|
||||
v = sumshifted[162:109];
|
||||
@ -87,38 +87,50 @@ logic tmp,tmp1,tmp2,tmp3;
|
||||
end
|
||||
|
||||
end else begin // extract normalized bits
|
||||
sumshifttmp = sumshift - 2;
|
||||
sumshifttmp = {1'b0,sumshift} - 2;
|
||||
sumshifted = sumshifttmp[9] ? sum : sum << sumshifttmp;
|
||||
tmp1 = (sumshifted[163] & ~zdenorm & ~sumshifttmp[9]);
|
||||
tmp2 = (zdenorm | sumshifttmp[9] || sumshifted[162]);
|
||||
tmp1 = (sumshifted[163] & ~sumshifttmp[9]);
|
||||
tmp2 = (sumshifttmp[9] || sumshifted[162]);
|
||||
tmp3 = sumshifted[161];
|
||||
tmp4 = sumshifted[160];
|
||||
tmp5 = sumshifted[159];
|
||||
// for some reason use exp = zexp + {0,1,2}
|
||||
// the book says exp = zexp + {-1,0,1}
|
||||
if(sumshiftzero) begin
|
||||
v = sum[162:109];
|
||||
sticky = sum[108:0] | bs;
|
||||
de0 = zexp;
|
||||
end else if(sumshifted[163] & ~zdenorm & ~sumshifttmp[9])begin
|
||||
end else if(sumshifted[163] & ~sumshifttmp[9])begin
|
||||
v = sumshifted[162:109];
|
||||
sticky = (|sumshifted[108:0]) | bs;
|
||||
de0 = zexp +2;
|
||||
end else if (zdenorm | sumshifttmp[9] || sumshifted[162]) begin
|
||||
end else if ((sumshifttmp[9] & sumshift[0]) || sumshifted[162]) begin
|
||||
v = sumshifted[161:108];
|
||||
sticky = (|sumshifted[107:0]) | bs;
|
||||
de0 = zexp+1;
|
||||
end else if (sumshifted[161]) begin
|
||||
end else if (sumshifted[161] || (sumshifttmp[9] & sumshift[1])) begin
|
||||
v = sumshifted[160:107];
|
||||
sticky = (|sumshifted[106:0]) | bs;
|
||||
//de0 = zexp-1;
|
||||
de0 = zexp;
|
||||
end else begin
|
||||
end else if(sumshifted[160]) begin
|
||||
v = sumshifted[159:106];
|
||||
sticky = (|sumshifted[105:0]) | bs;
|
||||
//de0 = zexp-1;
|
||||
de0 = zexp-1;
|
||||
end else if(sumshifted[159]) begin
|
||||
v = sumshifted[158:105];
|
||||
sticky = (|sumshifted[104:0]) | bs;
|
||||
//de0 = zexp-1;
|
||||
de0 = zexp-2;
|
||||
end else begin
|
||||
v = sumshifted[160:107];
|
||||
sticky = (|sumshifted[106:0]) | bs;
|
||||
//de0 = zexp-1;
|
||||
de0 = zexp;
|
||||
end
|
||||
|
||||
resultdenorm = 0;
|
||||
resultdenorm = ~(|de0);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
@ -1,11 +1,16 @@
|
||||
8020007ffdffffff 9beffff7fff7fffe 000ffffffff7fffe 0000000000000000 000ffffffff7fffe Wrong zdenorm unflw 475303
|
||||
3cafffffffffffff 3fd0000000000000 3cafffffffffffff 3c8ffffffffffffb 3cb3ffffffffffff Wrong 706913
|
||||
bfbfffff007fffff 000fffffffffffff 000bffffffc00000 0015000007dc0000 000a00000fb80000 Wrong ydenorm zdenorm 1675647
|
||||
00114508bde544e1 3caffffffffffffe 800010000003fffe 801008000001fffe 800010000003fffd Wrong zdenorm 2310057
|
||||
800ffffffdffffff bfcffe00003ffffe 800ffff01ffffffe 80160018103bfbff 800c00302077f7ff Wrong xdenorm zdenorm 2475205
|
||||
bcafffffffffffff 3fd0000000000001 bcafffffffffffff bc8ffffffffffffd bcb4000000000000 Wrong 3776249
|
||||
bfc0000000800008 43d0001000000002 c3cffffbffff8000 c3a00000007e008a c3d20000000fc011 Wrong 3804445
|
||||
bfefffffffffffff 3fefffffffffffff bff0000000000001 b950000000000000 c000000000000000 Wrong 4338155
|
||||
37ea3353806450ba bffffffffffffffe b803fffffffff7ff b7c19a9c032205b3 b8108cd4e019102e Wrong 5143755
|
||||
8010000000803fff 3ff0000000000001 000fffe07fffffff fff0000000000000 8000001f80804001 Wrong zdenorm w=-inf 5246469
|
||||
b7fffff80000001f 001ffffffffffffe 800fffffffff07ff 8000000000000000 800fffffffff07ff Wrong w=-zero zdenorm unflw 5723787
|
||||
0010000000000000 bf4fdffffff7fffe 800ffffffffffffe 800003fbfffffefe 801003fbfffffefe Wrong zdenorm 308227
|
||||
0010000000000000 be6fffffbffffff7 8000000000000000 800000001fffffc0 800000000fffffe0 Wrong 313753
|
||||
001ffffffffffffe 3fddfbffffffffff 000ffffffffffffe 000efdfffffffffd 001efdfffffffffd Wrong zdenorm 551371
|
||||
3befe000ffffffff 800ffffffffffffe 0000000000000000 0000000000000000 8000000000000000 Wrong ydenorm unflw 665575
|
||||
000007fffffffffe 3f6ffffffe01fffe 000ffffffffffffe 00000007ffffff7e 00100007ffffff7e Wrong xdenorm zdenorm 768727
|
||||
3fdffffffffffffe 000ffffffffffffe 8000000000000001 7feffffffffffff6 0007fffffffffffe Wrong ydenorm zdenorm 1049939
|
||||
7fe0000000000001 4000000000000000 ffefffffffffffff 7ff0000000000000 7cb8000000000000 Wrong w=+inf 2602745
|
||||
000fff000000000f 3ff00800001fffff 8010000000000000 7f7bfe007ff8381e 000006ff801ffe0e Wrong xdenorm 3117277
|
||||
8000000000000001 40211275ffe5ee3c 0000000000000001 fcfe24ebffcbdc78 8000000000000008 Wrong xdenorm zdenorm 3148591
|
||||
801fffffffffffff bfdffffffffffffe 0000000000021fff 0000000000021ffe 0010000000021ffe Wrong zdenorm 3537867
|
||||
801ffffffffffffe 0010000000000001 0000000000000000 0000000000000000 8000000000000000 Wrong unflw 3564269
|
||||
bca0000000000001 000fffffc000001e 8000000000000000 8000000000000001 8000000000000000 Wrong ydenorm 3717769
|
||||
bcafffffffffffff 800ffffffffffffe 8000000000000000 0000000000000002 0000000000000001 Wrong ydenorm 3807413
|
||||
7fec5fed92358a74 400000001bffffff ffefc0003ffffffe 7ff0000000000000 7fe8ffdb47bad466 Wrong w=+inf 3889689
|
||||
bfdfffffffffffff 3fdf1f3616aa73e1 3fd0000000000001 3fd07064f4aac611 3f7c193d2ab1843f Wrong 4099063
|
||||
3fd07dfffffffffe 8010000000000001 0000000000000001 ffe07dfffffffffb 80041f7fffffffff Wrong zdenorm 4716133
|
||||
|
||||
Binary file not shown.
@ -26,13 +26,13 @@ void main() {
|
||||
char ans[81];
|
||||
char flags[3];
|
||||
int rn,rz,rm,rp;
|
||||
long stop = 5723787;
|
||||
long stop = 4099063;
|
||||
int debug = 1;
|
||||
//my_string = (char *) malloc (nbytes + 1);
|
||||
//bytes_read = getline (&my_string, &nbytes, stdin);
|
||||
|
||||
|
||||
for(n=0; n < 2013; n++) {//613 for 10000
|
||||
for(n=0; n < 613; n++) {//613 for 10000
|
||||
if(getline(&ln,&nbytes,fp) < 0 || feof(fp)) break;
|
||||
if(k == stop && debug == 1) break;
|
||||
k++;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,476 +0,0 @@
|
||||
`include "../../../config/rv64icfd/wally-config.vh"
|
||||
|
||||
module fputop (
|
||||
input logic [2:0] FrmD,
|
||||
input logic reset,
|
||||
input logic clear,
|
||||
input logic clk,
|
||||
input logic [31:0] InstrD,
|
||||
input logic [`XLEN-1:0] SrcAE,
|
||||
input logic [`XLEN-1:0] SrcAW,
|
||||
output logic [31:0] FSROutW,
|
||||
output logic DivSqrtDoneE,
|
||||
output logic FInvalInstrD,
|
||||
output logic [`XLEN-1:0] FPUResultW);
|
||||
|
||||
//NOTE:
|
||||
//For readability and ease of modification, logic signals will be
|
||||
//instantiated as they occur within the pipeline. This will keep local
|
||||
//signals, modules, and combinational logic closely defined.
|
||||
|
||||
//used for OSU DP-size hardware to wally XLEN interfacing
|
||||
integer XLENDIFF;
|
||||
assign XLENDIFF = `XLEN - 64;
|
||||
integer XLENDIFFN;
|
||||
assign XLENDIFFN = 63 - `XLEN;
|
||||
|
||||
//#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#
|
||||
//BEGIN PIPELINE CONTROL LOGIC
|
||||
//
|
||||
|
||||
logic PipeEnableDE;
|
||||
logic PipeEnableEM;
|
||||
logic PipeEnableMW;
|
||||
logic PipeClearDE;
|
||||
logic PipeClearEM;
|
||||
logic PipeClearMW;
|
||||
|
||||
//temporarily assign pipe clear and enable signals
|
||||
//to never flush & always be running
|
||||
assign PipeClear = 1'b0;
|
||||
assign PipeEnable = 1'b1;
|
||||
always_comb begin
|
||||
|
||||
PipeEnableDE = PipeEnable;
|
||||
PipeEnableEM = PipeEnable;
|
||||
PipeEnableMW = PipeEnable;
|
||||
PipeClearDE = PipeClear;
|
||||
PipeClearEM = PipeClear;
|
||||
PipeClearMW = PipeClear;
|
||||
|
||||
end
|
||||
|
||||
//
|
||||
//END PIPELINE CONTROL LOGIC
|
||||
//#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#
|
||||
|
||||
//#########################################
|
||||
//BEGIN DECODE STAGE
|
||||
//
|
||||
|
||||
//wally-spec D stage control logic signal instantiation
|
||||
logic IllegalFPUInstrFaultD;
|
||||
logic FRegWriteD;
|
||||
logic [2:0] FResultSelD;
|
||||
//logic [2:0] FrmD;
|
||||
logic PD;
|
||||
logic DivSqrtStartD;
|
||||
logic [3:0] OpCtrlD;
|
||||
logic WriteIntD;
|
||||
|
||||
//top-level controller for FPU
|
||||
fctrl ctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Rs1D(InstrD[19:15]), .FrmW(InstrD[14:12]), .WriteEnD(FRegWriteD), .DivSqrtStartD(DivSqrtStartD), .WriteSelD(FResultSelD), .OpCtrlD(OpCtrlD), .FmtD(PD), .WriteIntD(WriteIntD));
|
||||
|
||||
//instantiation of D stage regfile signals (includes some W stage signals
|
||||
//for easy reference)
|
||||
logic [2:0] FrmW;
|
||||
logic WriteEnW;
|
||||
logic [4:0] RdW, Rs1D, Rs2D, Rs3D;
|
||||
logic [`XLEN-1:0] WriteDataW;
|
||||
logic [`XLEN-1:0] ReadData1D, ReadData2D, ReadData3D;
|
||||
|
||||
//regfile instantiation
|
||||
freg3adr fpregfile (FrmW, reset, PipeClear, clk, RdW, WriteEnW, Rs1D, Rs2D, Rs3D, WriteDataW, ReadData1D, ReadData2D, ReadData3D);
|
||||
|
||||
always_comb begin
|
||||
FrmW = InstrD[14:12];
|
||||
end
|
||||
|
||||
//
|
||||
//END DECODE STAGE
|
||||
//#########################################
|
||||
|
||||
//*****************************************
|
||||
//BEGIN D/E PIPE
|
||||
//
|
||||
|
||||
//wally-spec E stage control logic signal instantiation
|
||||
logic FRegWriteE;
|
||||
logic [2:0] FResultSelE;
|
||||
logic [2:0] FrmE;
|
||||
logic PE;
|
||||
logic DivSqrtStartE;
|
||||
logic [3:0] OpCtrlE;
|
||||
|
||||
//instantiation of E stage regfile signals
|
||||
logic [4:0] RdE;
|
||||
logic [`XLEN-1:0] ReadData1E, ReadData2E, ReadData3E;
|
||||
|
||||
//instantiation of E/M stage div/sqrt signals
|
||||
logic DivSqrtDone, DivDenormM;
|
||||
logic [63:0] DivResultM;
|
||||
logic [4:0] DivFlagsM;
|
||||
logic [63:0] DivOp1, DivOp2;
|
||||
logic [2:0] DivFrm;
|
||||
logic DivOpType;
|
||||
logic DivP;
|
||||
logic DivOvEn, DivUnEn;
|
||||
logic DivStart;
|
||||
|
||||
//instantiate E stage FMA signals here
|
||||
|
||||
//instantiation of E stage add/cvt signals
|
||||
logic [63:0] AddSumE, AddSumTcE;
|
||||
logic [3:0] AddSelInvE;
|
||||
logic [10:0] AddExpPostSumE;
|
||||
logic AddCorrSignE, AddOp1NormE, AddOp2NormE, AddOpANormE, AddOpBNormE, AddInvalidE;
|
||||
logic AddDenormInE, AddSwapE, AddNormOvflowE, AddSignAE;
|
||||
logic [63:0] AddFloat1E, AddFloat2E;
|
||||
logic [10:0] AddExp1DenormE, AddExp2DenormE, AddExponentE;
|
||||
logic [63:0] AddOp1E, AddOp2E;
|
||||
logic [2:0] AddRmE;
|
||||
logic [3:0] AddOpTypeE;
|
||||
logic AddPE, AddOvEnE, AddUnEnE;
|
||||
|
||||
//instantiation of E stage cmp signals
|
||||
logic [7:0] WE, XE;
|
||||
logic ANaNE, BNaNE, AzeroE, BzeroE;
|
||||
logic [63:0] CmpOp1E, CmpOp2E;
|
||||
logic [1:0] CmpSelE;
|
||||
|
||||
//instantiation of E/M stage fsgn signals (due to bypass logic)
|
||||
logic [63:0] SgnOp1E, SgnOp2E;
|
||||
logic [1:0] SgnOpCodeE, SgnOpCodeM;
|
||||
logic [63:0] SgnResultE, SgnResultM;
|
||||
logic [4:0] SgnFlagsE, SgnFlagsM;
|
||||
|
||||
//*****************
|
||||
//fpregfile D/E pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) (clk, reset, PipeClearDE, PipeEnableDE, ReadData1D, ReadData1E);
|
||||
flopenrc #(64) (clk, reset, PipeClearDE, PipeEnableDE, ReadData2D, ReadData2E);
|
||||
flopenrc #(64) (clk, reset, PipeClearDE, PipeEnableDE, ReadData3D, ReadData3E);
|
||||
|
||||
//*****************
|
||||
//other D/E pipe registers
|
||||
//*****************
|
||||
flopenrc #(1) (clk, reset, PipeClearDE, PipeEnableDE, FRegWriteD, FRegWriteE);
|
||||
flopenrc #(3) (clk, reset, PipeClearDE, PipeEnableDE, FResultsSelD, FResultsSelE);
|
||||
flopenrc #(3) (clk, reset, PipeClearDE, PipeEnableDE, FrmD, FrmE);
|
||||
flopenrc #(1) (clk, reset, PipeClearDE, PipeEnableDE, PD, PE);
|
||||
flopenrc #(4) (clk, reset, PipeClearDE, PipeEnableDE, OpCtrlD, OpCtrlE);
|
||||
flopenrc #(1) (clk, reset, PipeClearDE, PipeEnableDE, DivSqrtStartD, DivSqrtStartE);
|
||||
|
||||
//
|
||||
//END D/E PIPE
|
||||
//*****************************************
|
||||
|
||||
//#########################################
|
||||
//BEGIN EXECUTION STAGE
|
||||
//
|
||||
|
||||
//fma1 ();
|
||||
|
||||
//first and only instance of floating-point divider
|
||||
fpdivsqrt (DivSqrtDone, DivResultM, DivFlagsM, DivDenormM, DivOp1, DivOp2, DivFrm, DivOpType, DivP, DivOvEn, DivUnEn, DivStart, reset, clk);
|
||||
|
||||
//first of two-stage instance of floating-point add/cvt unit
|
||||
fpaddcvt1 fpadd1 (AddSumE, AddSumTcE, AddSelInvE, AddExpPostSumE, AddCorrSignE, AddOp1NormE, AddOp2NormE, AddOpANormE, AddOpBNormE, AddInvalidE, AddDenormInE, AddConvertE, AddSwapE, AddNormOvflowE, AddSignAE, AddFloat1E, AddFloat2E, AddExp1DenormE, AddExp2DenormE, AddExponentE, AddOp1E, AddOp2E, AddRmE, AddOpTypeE, AddPE, AddOvEnE, AddUnEnE);
|
||||
|
||||
//first of two-stage instance of floating-point comparator
|
||||
fpcmp1 fpcmp1 (WE, XE, ANaNE, BNaNE, AzeroE, BzeroE, CmpOp1E, CmpOp2E, CmpSelE);
|
||||
|
||||
//first and only instance of floating-point sign converter
|
||||
fpusgn fpsgn (SgnOpCodeE, SgnResultE, SgnFlagsE, SgnOp1, SgnOp2);
|
||||
|
||||
//interface between XLEN size datapath and double-precision sized
|
||||
//floating-point results
|
||||
//
|
||||
//define offsets for LSB zero extension or truncation
|
||||
always_comb begin
|
||||
|
||||
//truncate to 64 bits
|
||||
//(causes warning during compilation - case never reached)
|
||||
if(`XLEN > 64) begin
|
||||
DivOp1 <= ReadData1E[`XLEN:`XLEN-64];
|
||||
DivOp2 <= ReadData2E[`XLEN:`XLEN-64];
|
||||
AddOp1E <= ReadData1E[`XLEN:`XLEN-64];
|
||||
AddOp2E <= ReadData2E[`XLEN:`XLEN-64];
|
||||
CmpOp1E <= ReadData1E[`XLEN:`XLEN-64];
|
||||
CmpOp2E <= ReadData2E[`XLEN:`XLEN-64];
|
||||
SgnOp1E <= ReadData1E[`XLEN:`XLEN-64];
|
||||
SgnOp2E <= ReadData2E[`XLEN:`XLEN-64];
|
||||
end
|
||||
//zero extend to 64 bits
|
||||
else begin
|
||||
DivOp1 <= {ReadData1E,{64-`XLEN{1'b0}}};
|
||||
DivOp2 <= {ReadData2E,{64-`XLEN{1'b0}}};
|
||||
AddOp1E <= {ReadData1E,{64-`XLEN{1'b0}}};
|
||||
AddOp2E <= {ReadData2E,{64-`XLEN{1'b0}}};
|
||||
CmpOp1E <= {ReadData1E,{64-`XLEN{1'b0}}};
|
||||
CmpOp2E <= {ReadData2E,{64-`XLEN{1'b0}}};
|
||||
SgnOp1E <= {ReadData1E,{64-`XLEN{1'b0}}};
|
||||
SgnOp2E <= {ReadData2E,{64-`XLEN{1'b0}}};
|
||||
end
|
||||
|
||||
//assign op codes
|
||||
AddOpTypeE[3:0] <= OpCtrlE[3:0];
|
||||
CmpSelE[1:0] <= OpCtrlE[1:0];
|
||||
DivOpType <= OpCtrlE[0];
|
||||
SgnOpCodeE[1:0] <= OpCtrlE[1:0];
|
||||
|
||||
end
|
||||
|
||||
//E stage control signal interfacing between wally spec and OSU fp hardware
|
||||
//op codes
|
||||
|
||||
//
|
||||
//END EXECUTION STAGE
|
||||
//#########################################
|
||||
|
||||
//*****************************************
|
||||
//BEGIN E/M PIPE
|
||||
//
|
||||
|
||||
//wally-spec M stage control logic signal instantiation
|
||||
logic FRegWriteM;
|
||||
logic [2:0] FResultSelM;
|
||||
logic [2:0] FrmM;
|
||||
logic PM;
|
||||
logic [3:0] OpCtrlM;
|
||||
|
||||
//instantiate M stage FMA signals here
|
||||
|
||||
//instantiation of M stage regfile signals
|
||||
logic [4:0] RdM;
|
||||
logic [`XLEN-1:0] ReadData1M, ReadData2M, ReadData3M;
|
||||
|
||||
//instantiation of M stage add/cvt signals
|
||||
logic [63:0] AddResultM;
|
||||
logic [4:0] AddFlagsM;
|
||||
logic AddDenormM;
|
||||
logic [63:0] AddSumM, AddSumTcM;
|
||||
logic [3:0] AddSelInvM;
|
||||
logic [10:0] AddExpPostSumM;
|
||||
logic AddCorrSignM, AddOp1NormM, AddOp2NormM, AddOpANormM, AddOpBNormM, AddInvalidM;
|
||||
logic AddDenormInM, AddSwapM, AddNormOvflowM, AddSignAM;
|
||||
logic [63:0] AddFloat1M, AddFloat2M;
|
||||
logic [10:0] AddExp1DenormM, AddExp2DenormM, AddExponentM;
|
||||
logic [63:0] AddOp1M, AddOp2M;
|
||||
logic [2:0] AddRmM;
|
||||
logic [3:0] AddOpTypeM;
|
||||
logic AddPM, AddOvEnM, AddUnEnM;
|
||||
|
||||
//instantiation of M stage cmp signals
|
||||
logic CmpInvalidM;
|
||||
logic [1:0] CmpFCCM;
|
||||
logic [7:0] WM, XM;
|
||||
logic ANaNM, BNaNM, AzeroM, BzeroM;
|
||||
logic [63:0] CmpOp1M, CmpOp2M;
|
||||
logic [1:0] CmpSelM;
|
||||
|
||||
//*****************
|
||||
//fma E/M pipe registers
|
||||
//*****************
|
||||
|
||||
//*****************
|
||||
//fpadd E/M pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) (clk, reset, PipeClearEM, PipeEnableEM, AddSumE, AddSumM);
|
||||
flopenrc #(64) (clk, reset, PipeClearEM, PipeEnableEM, AddSumTcE, AddSumTcM);
|
||||
flopenrc #(4) (clk, reset, PipeClearEM, PipeEnableEM, AddSelInvE, AddSelInvM);
|
||||
flopenrc #(11) (clk, reset, PipeClearEM, PipeEnableEM, AddExpPostSumE, AddExpPostSumM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AddCorrSignE, AddCorrSignM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AddOp1NormE, AddOp1NormM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AddOp2NormE, AddOp2NormM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AddOpANormE, AddOpANormM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AddOpBNormE, AddOpBNormM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AddInvalidE, AddInvalidM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AddDenormInE, AddDenormInM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AddConvertE, AddConvertM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AddSwapE, AddSwapM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AddNormOvflowE, AddNormOvflowM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AddSignAE, AddSignM);
|
||||
flopenrc #(64) (clk, reset, PipeClearEM, PipeEnableEM, AddFloat1E, AddFloat1M);
|
||||
flopenrc #(64) (clk, reset, PipeClearEM, PipeEnableEM, AddFloat2E, AddFloat2M);
|
||||
flopenrc #(11) (clk, reset, PipeClearEM, PipeEnableEM, AddExp1DenormE, AddExp1DenormM);
|
||||
flopenrc #(11) (clk, reset, PipeClearEM, PipeEnableEM, AddExp2DenormE, AddExp2DenormM);
|
||||
flopenrc #(11) (clk, reset, PipeClearEM, PipeEnableEM, AddExponentE, AddExponentM);
|
||||
flopenrc #(64) (clk, reset, PipeClearEM, PipeEnableEM, AddOp1E, AddOp1M);
|
||||
flopenrc #(64) (clk, reset, PipeClearEM, PipeEnableEM, AddOp2E, AddOp2M);
|
||||
flopenrc #(3) (clk, reset, PipeClearEM, PipeEnableEM, AddRmE, AddRmM);
|
||||
flopenrc #(4) (clk, reset, PipeClearEM, PipeEnableEM, AddOpTypeE, AddOpTypeM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AddPE, AddPM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AddOvEnE, AddOvEnM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AddUnEnE, AddUnEnM);
|
||||
|
||||
//*****************
|
||||
//fpcmp E/M pipe registers
|
||||
//*****************
|
||||
flopenrc #(8) (clk, reset, PipeClearEM, PipeEnableEM, WE, WM);
|
||||
flopenrc #(8) (clk, reset, PipeClearEM, PipeEnableEM, XE, XM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, ANaNE, ANaNM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, BNaNE, BNaNM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, AzeroE, AzeroM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, BzeroE, BzeroM);
|
||||
flopenrc #(64) (clk, reset, PipeClearEM, PipeEnableEM, CmpOp1E, CmpOp1M);
|
||||
flopenrc #(64) (clk, reset, PipeClearEM, PipeEnableEM, CmpOp2E, CmpOp2M);
|
||||
flopenrc #(2) (clk, reset, PipeClearEM, PipeEnableEM, CmpSelE, CmpSelM);
|
||||
|
||||
//put this in for the event we want to delay fsgn - will otherwise bypass
|
||||
//*****************
|
||||
//fpsgn E/M pipe registers
|
||||
//*****************
|
||||
flopenrc #(2) (clk, reset, PipeClearEM, PipeEnableEM, SgnOpCodeE, SgnOpCodeM);
|
||||
flopenrc #(64) (clk, reset, PipeClearEM, PipeEnableEM, SgnResultE, SgnResultM);
|
||||
flopenrc #(5) (clk, reset, PipeClearEM, PipeEnableEM, SgnFlagsE, SgnFlagsM);
|
||||
|
||||
//*****************
|
||||
//other E/M pipe registers
|
||||
//*****************
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, FRegWriteE, FRegWriteM);
|
||||
flopenrc #(3) (clk, reset, PipeClearEM, PipeEnableEM, FResultsSelE, FResultsSelM);
|
||||
flopenrc #(3) (clk, reset, PipeClearEM, PipeEnableEM, FrmE, FrmM);
|
||||
flopenrc #(1) (clk, reset, PipeClearEM, PipeEnableEM, PE, PM);
|
||||
flopenrc #(4) (clk, reset, PipeClearEM, PipeEnableEM, OpCtrlE, OpCtrlM);
|
||||
|
||||
//
|
||||
//END E/M PIPE
|
||||
//*****************************************
|
||||
|
||||
//#########################################
|
||||
//BEGIN MEMORY STAGE
|
||||
//
|
||||
|
||||
//fma2 ();
|
||||
|
||||
//second instance of two-stage floating-point add/cvt unit
|
||||
fpaddcvt2 fpadd2 (AddResultM, AddFlagsM, AddDenormM, AddSumM, AddSumTcM, AddSelInvM, AddExpPostSumM, AddCorrSignM, AddOp1NormM, AddOp2NormM, AddOpANormM, AddOpBNormM, AddInvalidM, AddDenormInM, AddConvertM, AddSwapM, AddNormOvflowM, AddSignAM, AddFloat1M, AddFloat2M, AddExp1DenormM, AddExp2DenormM, AddExponentM, AddOp1M, AddOp2M, AddRmM, AddOpTypeM, AddPM, AddOvEnM, AddUnEnM);
|
||||
|
||||
//second instance of two-stage floating-point comparator
|
||||
fpcmp2 fpcmp2 (CmpInvalidM, CmpFCCM, ANaNM, BNaNM, AzeroM, BzeroM, WM, XM, CmpSelM, CmpOp1M, CmpOp2M);
|
||||
|
||||
//
|
||||
//END MEMORY STAGE
|
||||
//#########################################
|
||||
|
||||
|
||||
//*****************************************
|
||||
//BEGIN M/W PIPE
|
||||
//
|
||||
|
||||
//wally-spec W stage control logic signal instantiation
|
||||
logic FRegWriteW;
|
||||
logic [2:0] FResultSelW;
|
||||
logic PW;
|
||||
|
||||
//instantiate W stage fma signals here
|
||||
|
||||
//instantiation of W stage div/sqrt signals
|
||||
logic DivDenormW;
|
||||
logic [63:0] DivResultW;
|
||||
logic [4:0] DivFlagsW;
|
||||
|
||||
//instantiation of W stage regfile signals
|
||||
logic [`XLEN-1:0] ReadData1W, ReadData2W, ReadData3W;
|
||||
|
||||
//instantiation of W stage add/cvt signals
|
||||
logic [63:0] AddResultW;
|
||||
logic [4:0] AddFlagsW;
|
||||
logic AddDenormW;
|
||||
|
||||
//instantiation of W stage cmp signals
|
||||
logic CmpInvalidW;
|
||||
logic [1:0] CmpFCCW;
|
||||
|
||||
//*****************
|
||||
//fma M/W pipe registers
|
||||
//*****************
|
||||
|
||||
//*****************
|
||||
//fpdiv M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) (clk, reset, PipeClearMW, PipeEnableMW, DivResultM, DivResultW);
|
||||
flopenrc #(5) (clk, reset, PipeClearMW, PipeEnableMW, DivFlagsM, DivFlagsW);
|
||||
flopenrc #(1) (clk, reset, PipeClearMW, PipeEnableMW, DivDenormM, DivDenormW);
|
||||
|
||||
//*****************
|
||||
//fpadd M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) (clk, reset, PipeClearMW, PipeEnableMW, AddResultM, AddResultW);
|
||||
flopenrc #(5) (clk, reset, PipeClearMW, PipeEnableMW, AddFlagsM, AddFlagsW);
|
||||
flopenrc #(1) (clk, reset, PipeClearMW, PipeEnableMW, AddDenormM, AddDenormW);
|
||||
|
||||
//*****************
|
||||
//fpcmp M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(1) (clk, reset, PipeClearMW, PipeEnableMW, CmpInvalidM, CmpInvalidW);
|
||||
flopenrc #(2) (clk, reset, PipeClearMW, PipeEnableMW, CmpFCCM, CmpFCCW);
|
||||
|
||||
//*****************
|
||||
//fpsgn M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(64) (clk, reset, PipeClearMW, PipeEnableMw, SgnResultM, SgnResultW);
|
||||
flopenrc #(5) (clk, reset, PipeClearMw, PipeEnableMw, SgnFlagsM, SgnFlagsW);
|
||||
|
||||
//*****************
|
||||
//other M/W pipe registers
|
||||
//*****************
|
||||
flopenrc #(1) (clk, reset, PipeClearMW, PipeEnableMW, FRegWriteM, FRegWriteW);
|
||||
flopenrc #(3) (clk, reset, PipeClearMW, PipeEnableMW, FResultsSelM, FResultsSelW);
|
||||
flopenrc #(1) (clk, reset, PipeClearMW, PipeEnableMW, PM, PW);
|
||||
|
||||
////END M/W PIPE
|
||||
//*****************************************
|
||||
|
||||
|
||||
//#########################################
|
||||
//BEGIN WRITEBACK STAGE
|
||||
//
|
||||
|
||||
//flag signal mux via in-line ternaries
|
||||
logic [4:0] FPUFlagsW;
|
||||
//if bit 2 is active set to sign flags - otherwise:
|
||||
//iff bit one is high - if bit zero is active set to fma flags - otherwise
|
||||
//set to cmp flags
|
||||
//iff bit one is low - if bit zero is active set to add/cvt flags - otherwise
|
||||
//set to div/sqrt flags
|
||||
assign FPUFlagsW = (FResultSelW[2]) ? (SgnFlagsW) : (
|
||||
(FResultSelW[1]) ?
|
||||
( (FResultSelW[0]) ? (5'b00000) : ({CmpInvalidW,4'b0000}) )
|
||||
: ( (FResultSelW[0]) ? (AddFlagsW) : (DivFlagsW) )
|
||||
);
|
||||
|
||||
//result mux via in-line ternaries
|
||||
logic [63:0] FPUResultDirW;
|
||||
//the uses the same logic as for flag signals
|
||||
assign FPUResultDirW = (FResultSelW[2]) ? (SgnResultW) : (
|
||||
(FResultSelW[1]) ?
|
||||
( (FResultSelW[0]) ? (64'b0) : ({62'b0,CmpFCCW}) )
|
||||
: ( (FResultSelW[0]) ? (AddResultW) : (DivResultW) )
|
||||
);
|
||||
|
||||
//interface between XLEN size datapath and double-precision sized
|
||||
//floating-point results
|
||||
//
|
||||
//define offsets for LSB zero extension or truncation
|
||||
always_comb begin
|
||||
|
||||
//zero extension
|
||||
if(`XLEN > 64) begin
|
||||
FPUResultW <= {FPUResultDirW,{XLENDIFF{1'b0}}};
|
||||
end
|
||||
//truncate
|
||||
else begin
|
||||
FPUResultW <= FPUResultDirW[63:64-`XLEN];
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
//
|
||||
//END WRITEBACK STAGE
|
||||
//#########################################
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@ -26,19 +26,23 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module hazard(
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
// Detect hazards
|
||||
input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
|
||||
input logic LoadStallD, MulDivStallD, CSRRdStallD,
|
||||
input logic InstrStall, DataStall, ICacheStallF,
|
||||
input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
|
||||
input logic LoadStallD, MulDivStallD, CSRRdStallD,
|
||||
input logic InstrStall, DataStall, ICacheStallF,
|
||||
input logic DivBusyE,
|
||||
// Stall & flush outputs
|
||||
output logic StallF, StallD, StallE, StallM, StallW,
|
||||
output logic FlushF, FlushD, FlushE, FlushM, FlushW
|
||||
output logic StallF, StallD, StallE, StallM, StallW,
|
||||
output logic FlushF, FlushD, FlushE, FlushM, FlushW
|
||||
);
|
||||
|
||||
logic BranchFlushDE;
|
||||
logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
|
||||
logic FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW;
|
||||
|
||||
|
||||
// stalls and flushes
|
||||
// loads: stall for one cycle if the subsequent instruction depends on the load
|
||||
// branches and jumps: flush the next two instructions if the branch is taken in EXE
|
||||
@ -56,9 +60,10 @@ module hazard(
|
||||
assign StallFCause = CSRWritePendingDEM & ~(BranchFlushDE);
|
||||
assign StallDCause = (LoadStallD | MulDivStallD | CSRRdStallD) & ~(BranchFlushDE); // stall in decode if instruction is a load/mul/csr dependent on previous
|
||||
// assign StallDCause = LoadStallD | MulDivStallD | CSRRdStallD; // stall in decode if instruction is a load/mul/csr dependent on previous
|
||||
assign StallECause = 0;
|
||||
assign StallECause = DivBusyE;
|
||||
assign StallMCause = 0;
|
||||
assign StallWCause = DataStall | InstrStall;
|
||||
|
||||
|
||||
// Each stage stalls if the next stage is stalled or there is a cause to stall this stage.
|
||||
assign StallF = StallD | StallFCause;
|
||||
@ -68,15 +73,17 @@ module hazard(
|
||||
assign StallM = StallW | StallMCause;
|
||||
assign StallW = StallWCause;
|
||||
|
||||
//assign FirstUnstalledD = (~StallD & StallF & ~MulDivStallD);
|
||||
assign FirstUnstalledD = (~StallD & StallF);
|
||||
//assign FirstUnstalledE = (~StallE & StallD & ~MulDivStallD);
|
||||
assign FirstUnstalledE = (~StallE & StallD);
|
||||
assign FirstUnstalledM = (~StallM & StallE);
|
||||
assign FirstUnstalledW = (~StallW & StallM);;
|
||||
|
||||
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
|
||||
assign FlushF = BPPredWrongE;
|
||||
assign FlushD = FirstUnstalledD || BranchFlushDE; // PCSrcE |InstrStall | CSRWritePendingDEM | RetM | TrapM;
|
||||
assign FlushE = FirstUnstalledE || BranchFlushDE; //LoadStallD | PCSrcE | RetM | TrapM;
|
||||
assign FlushD = FirstUnstalledD || BranchFlushDE; // PCSrcE |InstrStall | CSRWritePendingDEM | RetM | TrapM;
|
||||
assign FlushE = FirstUnstalledE || BranchFlushDE; // LoadStallD | PCSrcE | RetM | TrapM;
|
||||
assign FlushM = FirstUnstalledM || RetM || TrapM;
|
||||
assign FlushW = FirstUnstalledW | TrapM;
|
||||
endmodule
|
||||
|
||||
@ -30,7 +30,7 @@ module forward(
|
||||
input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
|
||||
input logic MemReadE, MulDivE, CSRReadE,
|
||||
input logic RegWriteM, RegWriteW,
|
||||
input logic DivDoneW,
|
||||
input logic DivDoneE, DivBusyE,
|
||||
// Forwarding controls
|
||||
output logic [1:0] ForwardAE, ForwardBE,
|
||||
output logic LoadStallD, MulDivStallD, CSRRdStallD
|
||||
@ -50,7 +50,7 @@ module forward(
|
||||
|
||||
// Stall on dependent operations that finish in Mem Stage and can't bypass in time
|
||||
assign LoadStallD = MemReadE & ((Rs1D == RdE) | (Rs2D == RdE));
|
||||
assign MulDivStallD = MulDivE & ((Rs1D == RdE) | (Rs2D == RdE)) | MulDivE&~DivDoneW; // *** extend with stalls for divide
|
||||
assign MulDivStallD = MulDivE & ((Rs1D == RdE) | (Rs2D == RdE)) | MulDivE | DivBusyE; // *** extend with stalls for divide
|
||||
assign CSRRdStallD = CSRReadE & ((Rs1D == RdE) | (Rs2D == RdE));
|
||||
|
||||
endmodule
|
||||
|
||||
@ -56,8 +56,8 @@ module ieu (
|
||||
input logic FlushE, FlushM, FlushW,
|
||||
output logic LoadStallD, MulDivStallD, CSRRdStallD,
|
||||
output logic PCSrcE,
|
||||
input logic DivDoneW,
|
||||
|
||||
input logic DivDoneE,
|
||||
input logic DivBusyE,
|
||||
output logic CSRReadM, CSRWriteM, PrivilegedM,
|
||||
output logic CSRWritePendingDEM
|
||||
);
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
module div (Q, rem0, divdone, div0, N, D, clk, reset, start);
|
||||
module div (Q, rem0, done, divBusy, div0, N, D, clk, reset, start);
|
||||
|
||||
input logic [63:0] N, D;
|
||||
input logic clk;
|
||||
@ -33,9 +33,10 @@ module div (Q, rem0, divdone, div0, N, D, clk, reset, start);
|
||||
output logic [63:0] Q;
|
||||
output logic [63:0] rem0;
|
||||
output logic div0;
|
||||
output logic divdone;
|
||||
output logic done;
|
||||
output logic divBusy;
|
||||
|
||||
logic done;
|
||||
logic divdone;
|
||||
logic enable;
|
||||
logic state0;
|
||||
logic V;
|
||||
@ -86,14 +87,15 @@ module div (Q, rem0, divdone, div0, N, D, clk, reset, start);
|
||||
// FSM to control integer divider
|
||||
// assume inputs are postive edge and
|
||||
// datapath (divider) is negative edge
|
||||
fsm64 fsm1 (enablev, state0v, donev, divdonev, otfzerov,
|
||||
fsm64 fsm1 (enablev, state0v, donev, divdonev, otfzerov, divBusyv,
|
||||
start, div0, NumIter, ~clk, reset);
|
||||
|
||||
flopr #(1) rega (~clk, reset, donev, done);
|
||||
flopr #(1) regb (~clk, reset, divdonev, divdone);
|
||||
flopr #(1) regc (~clk, reset, otfzerov, otfzero);
|
||||
flopr #(1) regd (~clk, reset, enablev, enable);
|
||||
flopr #(1) rege (~clk, reset, state0v, state0);
|
||||
flopr #(1) rege (~clk, reset, state0v, state0);
|
||||
flopr #(1) regf (~clk, reset, divBusyv, divBusy);
|
||||
|
||||
// To obtain a correct remainder the last bit of the
|
||||
// quotient has to be aligned with a radix-r boundary.
|
||||
@ -460,7 +462,7 @@ endmodule // lz64
|
||||
|
||||
// FSM Control for Integer Divider
|
||||
|
||||
module fsm64 (en, state0, done, divdone, otfzero,
|
||||
module fsm64 (en, state0, done, divdone, otfzero, divBusy,
|
||||
start, error, NumIter, clk, reset);
|
||||
|
||||
input logic [5:0] NumIter;
|
||||
@ -473,7 +475,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
output logic en;
|
||||
output logic state0;
|
||||
output logic divdone;
|
||||
output logic otfzero;
|
||||
output logic otfzero;
|
||||
output logic divBusy;
|
||||
|
||||
logic LT, EQ;
|
||||
logic Divide0;
|
||||
@ -519,6 +522,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
begin
|
||||
otfzero = 1'b1;
|
||||
en = 1'b0;
|
||||
divBusy = 1'b0;
|
||||
state0 = 1'b0;
|
||||
divdone = 1'b0;
|
||||
done = 1'b0;
|
||||
@ -528,6 +532,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
en = 1'b1;
|
||||
divBusy = 1'b1;
|
||||
state0 = 1'b1;
|
||||
if (EQ)
|
||||
divdone = 1'b1;
|
||||
@ -540,7 +545,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end
|
||||
S1:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -564,6 +570,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
S2:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -587,6 +594,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
S3:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -610,6 +618,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
S4:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -633,6 +642,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
S5:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -656,6 +666,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
S6:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -678,7 +689,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S6
|
||||
S7:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -701,7 +713,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S7
|
||||
S8:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -725,6 +738,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
S9:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -747,7 +761,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S9
|
||||
S10:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -771,6 +786,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
S11:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -794,6 +810,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
S12:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -817,6 +834,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
S13:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -840,6 +858,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
S14:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -863,6 +882,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
S15:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -885,7 +905,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S15
|
||||
S16:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -908,7 +929,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S16
|
||||
S17:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -931,7 +953,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S17
|
||||
S18:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -954,7 +977,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S18
|
||||
S19:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -977,7 +1001,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S19
|
||||
S20:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1000,7 +1025,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S20
|
||||
S21:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1023,7 +1049,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S21
|
||||
S22:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1047,6 +1074,7 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
S23:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1069,7 +1097,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S23
|
||||
S24:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1092,7 +1121,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S24
|
||||
S25:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1115,7 +1145,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S25
|
||||
S26:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1138,7 +1169,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S26
|
||||
S27:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1161,7 +1193,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S27
|
||||
S28:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1184,7 +1217,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S28
|
||||
S29:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1207,7 +1241,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S29
|
||||
S30:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1230,7 +1265,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S30
|
||||
S31:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1253,7 +1289,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S31
|
||||
S32:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1276,7 +1313,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S32
|
||||
S33:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1299,7 +1337,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S33
|
||||
S34:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1322,7 +1361,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S34
|
||||
S35:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
if (LT|EQ)
|
||||
begin
|
||||
en = 1'b1;
|
||||
@ -1345,7 +1385,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S35
|
||||
S36:
|
||||
begin
|
||||
otfzero = 1'b1;
|
||||
otfzero = 1'b1;
|
||||
divBusy = 1'b1;
|
||||
state0 = 1'b0;
|
||||
done = 1'b1;
|
||||
if (EQ)
|
||||
@ -1362,7 +1403,8 @@ module fsm64 (en, state0, done, divdone, otfzero,
|
||||
end // case: S36
|
||||
default:
|
||||
begin
|
||||
otfzero = 1'b0;
|
||||
otfzero = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
en = 1'b0;
|
||||
state0 = 1'b0;
|
||||
done = 1'b0;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@ -8,8 +8,12 @@ int main() {
|
||||
uint64_t D;
|
||||
uint64_t Q;
|
||||
|
||||
N = 0xc9649f05a8e1a8bb;
|
||||
D = 0x82f6747f707af2c0;
|
||||
//N = 0xc9649f05a8e1a8bb;
|
||||
//D = 0x82f6747f707af2c0;
|
||||
//N = 0x10fd3dedadea5195;
|
||||
//D = 0xdf7f3844121bcc23;
|
||||
N = 0x4;
|
||||
D = 0xbfffffffffffffff;
|
||||
Q = N/D;
|
||||
|
||||
printf("N = %" PRIx64 "\n", N);
|
||||
|
||||
@ -1,21 +0,0 @@
|
||||
#include <stdio.h>
|
||||
#include <math.h>
|
||||
#include <inttypes.h>
|
||||
|
||||
int main() {
|
||||
|
||||
uint64_t N;
|
||||
uint64_t D;
|
||||
uint64_t Q;
|
||||
|
||||
N = 0xc9649f05a8e1a8bb;
|
||||
D = 0x82f6747f707af2c0;
|
||||
|
||||
printf("N = %" PRIx64 "\n", N);
|
||||
printf("D = %" PRIx64 "\n", D);
|
||||
printf("Q = %" PRIx64 "\n", Q);
|
||||
printf("R = %" PRIx64 "\n", N%D);
|
||||
|
||||
|
||||
|
||||
}
|
||||
@ -1,107 +1,67 @@
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 | 0000000000000000 0000000000000000 1 1
|
||||
c9649f05a8e1a8bb 82f6747f707af2c0 | 0000000000000000 0000000000000000 0 | 0000000000000001 466e2a863866b5fb 0 0
|
||||
c9649f05a8e1a8bb 82f6747f707af2c0 | 0000000000000000 0000000000000000 0 | 0000000000000001 466e2a863866b5fb 0 0
|
||||
c9649f05a8e1a8bb 82f6747f707af2c0 | 0000000000000000 0000000000000000 0 | 0000000000000001 466e2a863866b5fb 0 0
|
||||
c9649f05a8e1a8bb 82f6747f707af2c0 | 0000000000000000 0000000000000000 0 | 0000000000000001 466e2a863866b5fb 0 0
|
||||
c9649f05a8e1a8bb 82f6747f707af2c0 | 0000000000000000 0000000000000000 0 | 0000000000000001 466e2a863866b5fb 0 0
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 0000000000000000 0 | 0000000000000000 10fd3dedadea5195 1 0
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 0000000000000000 0 | 0000000000000000 10fd3dedadea5195 1 0
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 0000000000000000 0 | 0000000000000000 10fd3dedadea5195 1 0
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 0000000000000000 0 | 0000000000000000 10fd3dedadea5195 1 0
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 0000000000000000 0 | 0000000000000000 10fd3dedadea5195 1 0
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 0 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
|
||||
0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 0000000000000000 | 0000000000000000 10fd3dedadea5195 1 0
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 0000000000000000 | 0000000000000000 10fd3dedadea5195 1 0
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 0000000000000000 | 0000000000000000 10fd3dedadea5195 1 0
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 0000000000000000 | 0000000000000000 10fd3dedadea5195 1 0
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
10fd3dedadea5195 df7f3844121bcc23 | 0000000000000000 10fd3dedadea5195 | 0000000000000000 10fd3dedadea5195 1 1
|
||||
|
||||
@ -1,106 +0,0 @@
|
||||
module shifter_l64 (Z, A, Shift);
|
||||
|
||||
input logic [63:0] A;
|
||||
input logic [5:0] Shift;
|
||||
|
||||
logic [63:0] stage1;
|
||||
logic [63:0] stage2;
|
||||
logic [63:0] stage3;
|
||||
logic [63:0] stage4;
|
||||
logic [63:0] stage5;
|
||||
logic [31:0] thirtytwozeros = 32'h0;
|
||||
logic [15:0] sixteenzeros = 16'h0;
|
||||
logic [ 7:0] eightzeros = 8'h0;
|
||||
logic [ 3:0] fourzeros = 4'h0;
|
||||
logic [ 1:0] twozeros = 2'b00;
|
||||
logic onezero = 1'b0;
|
||||
|
||||
output logic [63:0] Z;
|
||||
|
||||
mux21x64 mx01(stage1, A, {A[31:0], thirtytwozeros}, Shift[5]);
|
||||
mux21x64 mx02(stage2, stage1, {stage1[47:0], sixteenzeros}, Shift[4]);
|
||||
mux21x64 mx03(stage3, stage2, {stage2[55:0], eightzeros}, Shift[3]);
|
||||
mux21x64 mx04(stage4, stage3, {stage3[59:0], fourzeros}, Shift[2]);
|
||||
mux21x64 mx05(stage5, stage4, {stage4[61:0], twozeros}, Shift[1]);
|
||||
mux21x64 mx06(Z, stage5, {stage5[62:0], onezero}, Shift[0]);
|
||||
|
||||
endmodule // shifter_l64
|
||||
|
||||
module shifter_r64 (Z, A, Shift);
|
||||
|
||||
input logic [63:0] A;
|
||||
input logic [5:0] Shift;
|
||||
|
||||
logic [63:0] stage1;
|
||||
logic [63:0] stage2;
|
||||
logic [63:0] stage3;
|
||||
logic [63:0] stage4;
|
||||
logic [63:0] stage5;
|
||||
logic [31:0] thirtytwozeros = 32'h0;
|
||||
logic [15:0] sixteenzeros = 16'h0;
|
||||
logic [ 7:0] eightzeros = 8'h0;
|
||||
logic [ 3:0] fourzeros = 4'h0;
|
||||
logic [ 1:0] twozeros = 2'b00;
|
||||
logic onezero = 1'b0;
|
||||
|
||||
output logic [63:0] Z;
|
||||
|
||||
mux21x64 mx01(stage1, A, {thirtytwozeros, A[63:32]}, Shift[5]);
|
||||
mux21x64 mx02(stage2, stage1, {sixteenzeros, stage1[63:16]}, Shift[4]);
|
||||
mux21x64 mx03(stage3, stage2, {eightzeros, stage2[63:8]}, Shift[3]);
|
||||
mux21x64 mx04(stage4, stage3, {fourzeros, stage3[63:4]}, Shift[2]);
|
||||
mux21x64 mx05(stage5, stage4, {twozeros, stage4[63:2]}, Shift[1]);
|
||||
mux21x64 mx06(Z, stage5, {onezero, stage5[63:1]}, Shift[0]);
|
||||
|
||||
endmodule // shifter_r64
|
||||
|
||||
module shifter_l32 (Z, A, Shift);
|
||||
|
||||
input logic [31:0] A;
|
||||
input logic [4:0] Shift;
|
||||
|
||||
logic [31:0] stage1;
|
||||
logic [31:0] stage2;
|
||||
logic [31:0] stage3;
|
||||
logic [31:0] stage4;
|
||||
logic [15:0] sixteenzeros = 16'h0;
|
||||
logic [ 7:0] eightzeros = 8'h0;
|
||||
logic [ 3:0] fourzeros = 4'h0;
|
||||
logic [ 1:0] twozeros = 2'b00;
|
||||
logic onezero = 1'b0;
|
||||
|
||||
output logic [31:0] Z;
|
||||
|
||||
mux21x32 mx01(stage1, A, {A[15:0], sixteenzeros}, Shift[4]);
|
||||
mux21x32 mx02(stage2, stage1, {stage1[23:0], eightzeros}, Shift[3]);
|
||||
mux21x32 mx03(stage3, stage2, {stage2[27:0], fourzeros}, Shift[2]);
|
||||
mux21x32 mx04(stage4, stage3, {stage3[29:0], twozeros}, Shift[1]);
|
||||
mux21x32 mx05(Z , stage4, {stage4[30:0], onezero}, Shift[0]);
|
||||
|
||||
endmodule // shifter_l32
|
||||
|
||||
module shifter_r32 (Z, A, Shift);
|
||||
|
||||
input logic [31:0] A;
|
||||
input logic [4:0] Shift;
|
||||
|
||||
logic [31:0] stage1;
|
||||
logic [31:0] stage2;
|
||||
logic [31:0] stage3;
|
||||
logic [31:0] stage4;
|
||||
logic [15:0] sixteenzeros = 16'h0;
|
||||
logic [ 7:0] eightzeros = 8'h0;
|
||||
logic [ 3:0] fourzeros = 4'h0;
|
||||
logic [ 1:0] twozeros = 2'b00;
|
||||
logic onezero = 1'b0;
|
||||
|
||||
output logic [31:0] Z;
|
||||
|
||||
mux21x32 mx01(stage1, A, {sixteenzeros, A[31:16]}, Shift[4]);
|
||||
mux21x32 mx02(stage2, stage1, {eightzeros, stage1[31:8]}, Shift[3]);
|
||||
mux21x32 mx03(stage3, stage2, {fourzeros, stage2[31:4]}, Shift[2]);
|
||||
mux21x32 mx04(stage4, stage3, {twozeros, stage3[31:2]}, Shift[1]);
|
||||
mux21x32 mx05(Z , stage4, {onezero, stage4[31:1]}, Shift[0]);
|
||||
|
||||
endmodule // shifter_r32
|
||||
|
||||
@ -15,9 +15,18 @@ module tb;
|
||||
integer desc3;
|
||||
integer i;
|
||||
|
||||
logic [7:0] count [0:15];
|
||||
logic [7:0] count [0:15];
|
||||
|
||||
bit [63:0] Ncomp;
|
||||
bit [63:0] Dcomp;
|
||||
bit [63:0] Qcomp;
|
||||
bit [63:0] Rcomp;
|
||||
|
||||
int64div dut (Q, done, divdone, rem, div0, N, D, clk, reset, start);
|
||||
assign Ncomp = N;
|
||||
assign Dcomp = D;
|
||||
assign Qcomp = Ncomp/Dcomp;
|
||||
assign Rcomp = Ncomp%Dcomp;
|
||||
|
||||
initial
|
||||
begin
|
||||
@ -29,7 +38,20 @@ module tb;
|
||||
begin
|
||||
#800 $finish;
|
||||
end
|
||||
|
||||
|
||||
initial
|
||||
begin
|
||||
handle3 = $fopen("div64.out");
|
||||
desc3 = handle3;
|
||||
end
|
||||
|
||||
always
|
||||
begin
|
||||
desc3 = handle3;
|
||||
#5 $fdisplay(desc3, "%h %h | %h %h | %h %h %b %b",
|
||||
N, D, Q, rem, Qcomp, Rcomp,
|
||||
(Q==Qcomp), (rem==Rcomp));
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
@ -38,10 +60,8 @@ module tb;
|
||||
#0 start = 1'b0;
|
||||
#0 reset = 1'b1;
|
||||
#22 reset = 1'b0;
|
||||
//#25 N = 64'h0000_0000_9830_07C0;
|
||||
//#0 D = 64'h0000_0000_0000_000C;
|
||||
#25 N = 64'h0000_0000_06b9_7b0d;
|
||||
#0 D = 64'h0000_0000_46df_998d;
|
||||
#25 N = 64'h10fd_3ded_adea_5195;
|
||||
#0 D = 64'hdf7f_3844_121b_cc23;
|
||||
#0 start = 1'b1;
|
||||
#50 start = 1'b0;
|
||||
|
||||
|
||||
@ -36,9 +36,10 @@ module muldiv (
|
||||
// Writeback stage
|
||||
output logic [`XLEN-1:0] MulDivResultW,
|
||||
// Divide Done
|
||||
output logic DivDoneW,
|
||||
output logic DivDoneE,
|
||||
output logic DivBusyE,
|
||||
// hazards
|
||||
input logic StallM, StallW, FlushM, FlushW
|
||||
input logic StallE, StallM, StallW, FlushM, FlushW
|
||||
);
|
||||
|
||||
generate
|
||||
@ -47,15 +48,43 @@ module muldiv (
|
||||
logic [`XLEN-1:0] PrelimResultE;
|
||||
logic [`XLEN-1:0] QuotE, RemE;
|
||||
logic [`XLEN*2-1:0] ProdE;
|
||||
|
||||
logic DivStartE;
|
||||
logic startDivideE;
|
||||
|
||||
logic enable_q, gclk;
|
||||
|
||||
logic [2:0] Funct3E_Q;
|
||||
|
||||
|
||||
// Multiplier
|
||||
mul mul(.*);
|
||||
// Divide
|
||||
div div (QuotE, RemE, DivDoneE, div0error, SrcAE, SrcBE, clk, reset, MulDivE);
|
||||
|
||||
// *** replace this clock gater
|
||||
always @(~clk) begin
|
||||
enable_q <= ~StallM;
|
||||
end
|
||||
assign gclk = enable_q & clk;
|
||||
|
||||
div div (QuotE, RemE, DivDoneE, DivBusyE, div0error, SrcAE, SrcBE, gclk, reset, startDivideE);
|
||||
|
||||
// Added for debugging of start signal for divide
|
||||
assign startDivideE = MulDivE&DivStartE&~DivBusyE;
|
||||
|
||||
// capture the start control signals since they are not held constant.
|
||||
flopenrc #(3) funct3ereg (.d(Funct3E),
|
||||
.q(Funct3E_Q),
|
||||
.en(DivStartE),
|
||||
.clear(DivDoneE),
|
||||
.reset(reset),
|
||||
.clk(clk));
|
||||
|
||||
|
||||
// Select result
|
||||
always_comb
|
||||
case (Funct3E)
|
||||
// case (DivDoneE ? Funct3E_Q : Funct3E)
|
||||
case (Funct3E)
|
||||
3'b000: PrelimResultE = ProdE[`XLEN-1:0];
|
||||
3'b001: PrelimResultE = ProdE[`XLEN*2-1:`XLEN];
|
||||
3'b010: PrelimResultE = ProdE[`XLEN*2-1:`XLEN];
|
||||
@ -64,6 +93,19 @@ module muldiv (
|
||||
3'b101: PrelimResultE = QuotE;
|
||||
3'b110: PrelimResultE = RemE;
|
||||
3'b111: PrelimResultE = RemE;
|
||||
endcase // case (Funct3E)
|
||||
|
||||
// Start Divide process
|
||||
always_comb
|
||||
case (Funct3E)
|
||||
3'b000: DivStartE = 1'b0;
|
||||
3'b001: DivStartE = 1'b0;
|
||||
3'b010: DivStartE = 1'b0;
|
||||
3'b011: DivStartE = 1'b0;
|
||||
3'b100: DivStartE = 1'b1;
|
||||
3'b101: DivStartE = 1'b1;
|
||||
3'b110: DivStartE = 1'b1;
|
||||
3'b111: DivStartE = 1'b1;
|
||||
endcase
|
||||
|
||||
// Handle sign extension for W-type instructions
|
||||
|
||||
@ -84,11 +84,17 @@ module wallypipelinedhart (
|
||||
logic PCSrcE;
|
||||
logic CSRWritePendingDEM;
|
||||
logic LoadStallD, MulDivStallD, CSRRdStallD;
|
||||
logic DivDoneW;
|
||||
logic DivDoneE;
|
||||
logic DivBusyE;
|
||||
logic [4:0] SetFflagsM;
|
||||
logic [2:0] FRM_REGW;
|
||||
logic DivDoneW;
|
||||
logic FloatRegWriteW;
|
||||
logic SquashSCW;
|
||||
logic [31:0] FSROutW;
|
||||
logic DivSqrtDoneE;
|
||||
logic FInvalInstrD;
|
||||
logic [`XLEN-1:0] FPUResultW;
|
||||
|
||||
// memory management unit signals
|
||||
logic ITLBWriteF, DTLBWriteM;
|
||||
@ -143,16 +149,17 @@ module wallypipelinedhart (
|
||||
|
||||
|
||||
muldiv mdu(.*); // multiply and divide unit
|
||||
/* fpu fpu(.*); // floating point unit
|
||||
*/
|
||||
|
||||
hazard hzu(.*); // global stall and flush control
|
||||
|
||||
// Priveleged block operates in M and W stages, handling CSRs and exceptions
|
||||
privileged priv(.*);
|
||||
|
||||
|
||||
fpu fpu(.*); // floating point unit
|
||||
// add FPU here, with SetFflagsM, FRM_REGW
|
||||
// presently stub out SetFlagsM and FloatRegWriteW
|
||||
assign SetFflagsM = 0;
|
||||
assign FloatRegWriteW = 0;
|
||||
//assign SetFflagsM = 0;
|
||||
//assign FloatRegWriteW = 0;
|
||||
|
||||
endmodule
|
||||
|
||||
@ -370,7 +370,7 @@ string tests32i[] = {
|
||||
if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
|
||||
end
|
||||
// tests = {tests64a, tests};
|
||||
tests = {tests, tests64p};
|
||||
// tests = {tests, tests64p};
|
||||
end else begin // RV32
|
||||
// *** add the 32 bit bp tests
|
||||
tests = {tests32i};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user