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Fix extraneous page fault stall

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This commit is contained in:
Thomas Fleming 2021-04-03 21:28:24 -04:00
parent 35ba6f741b
commit e04ad8f304
4 changed files with 23 additions and 31 deletions
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10
wally-pipelined/src/ebu/ahblite.sv
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@ -136,13 +136,13 @@ module ahblite (
// stall signals
// Note that we need to extend both stalls when MMUTRANSLATE goes to idle,
// since translation might not be complete.
assign #2 DataStall = ~TrapM && ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) ||
(NextBusState == MMUTRANSLATE) || (BusState == MMUTRANSLATE));
assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) ||
(NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete)); // && ~TrapM
// *** Could get finer grained stalling if we distinguish between MMU
// instruction address translation and data address translation
assign #1 InstrStall = ~TrapM && ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
(NextBusState == MMUTRANSLATE) || (BusState == MMUTRANSLATE));
assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
(NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete)); // && ~TrapM
// bus outputs
assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||

10
wally-pipelined/src/ebu/pagetablewalker.sv
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@ -116,7 +116,7 @@ module pagetablewalker (
// unswizzle PTE bits
assign {Dirty, Accessed, Global, User,
Executable, Writable, Readable, Valid} = CurrentPTE[7:0];
// Assign PTE descriptors common across all XLEN values
assign LeafPTE = Executable | Writable | Readable;
assign ValidPTE = Valid && ~(Writable && ~Readable);
@ -195,6 +195,8 @@ module pagetablewalker (
assign ITLBWriteF = ~DTLBMissM; // Prefer data over instructions
end
FAULT: begin
assign TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
assign MMUTranslationComplete = '1;
assign InstrPageFaultM = ~DTLBMissM;
assign LoadPageFaultM = DTLBMissM && ~MemStore;
assign StorePageFaultM = DTLBMissM && MemStore;
@ -206,8 +208,6 @@ module pagetablewalker (
// Capture page table entry from ahblite
flopenr #(32) ptereg(HCLK, ~HRESETn, MMUReady, MMUReadPTE, SavedPTE);
// *** Evil hack to get CurrentPTE a cycle early before it is saved.
// Todo: Is it evil?
mux2 #(32) ptemux(SavedPTE, MMUReadPTE, MMUReady, CurrentPTE);
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];
@ -300,6 +300,8 @@ module pagetablewalker (
assign ITLBWriteF = ~DTLBMissM; // Prefer data over instructions
end
FAULT: begin
assign TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
assign MMUTranslationComplete = '1;
assign InstrPageFaultM = ~DTLBMissM;
assign LoadPageFaultM = DTLBMissM && ~MemStore;
assign StorePageFaultM = DTLBMissM && MemStore;
@ -309,8 +311,6 @@ module pagetablewalker (
// Capture page table entry from ahblite
flopenr #(`XLEN) ptereg(HCLK, ~HRESETn, MMUReady, MMUReadPTE, SavedPTE);
// *** Evil hack to get CurrentPTE a cycle early before it is saved.
// Todo: Is it evil?
mux2 #(`XLEN) ptemux(SavedPTE, MMUReadPTE, MMUReady, CurrentPTE);
assign CurrentPPN = CurrentPTE[`PPN_BITS+9:10];

12
wally-pipelined/src/mmu/tlb.sv
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@ -132,16 +132,7 @@ module tlb #(parameter ENTRY_BITS = 3) (
tlb_ram #(ENTRY_BITS) ram(.*);
tlb_cam #(ENTRY_BITS, `VPN_BITS) cam(.*);
always_comb begin
assign PhysicalPageNumber = PageTableEntry[`PPN_BITS+9:10];
if (TLBHit) begin
assign PhysicalAddressFull = {PhysicalPageNumber, PageOffset};
end else begin
assign PhysicalAddressFull = '0; // *** Actual behavior; disabled until walker functioning
//assign PhysicalAddressFull = {2'b0, VirtualPageNumber, PageOffset} // *** pass through should be removed as soon as walker ready
end
end
assign PhysicalAddressFull = (TLBHit) ? {PhysicalPageNumber, PageOffset} : '0;
generate
if (`XLEN == 32) begin
@ -155,6 +146,7 @@ module tlb #(parameter ENTRY_BITS = 3) (
assign TLBMiss = ~TLBHit & ~TLBFlush & Translate & TLBAccess;
endmodule
// *** use actual flop notation instead of initialbegin and alwaysff
module tlb_ram #(parameter ENTRY_BITS = 3) (
input clk, reset,
input [ENTRY_BITS-1:0] VPNIndex, // Index to read from

22
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -65,7 +65,7 @@ module wallypipelinedhart (
logic [`XLEN-1:0] SrcAE, SrcBE;
logic [`XLEN-1:0] SrcAM;
logic [2:0] Funct3E;
// logic [31:0] InstrF;
// logic [31:0] InstrF;
logic [31:0] InstrD, InstrM;
logic [`XLEN-1:0] PCE, PCM, PCLinkE, PCLinkW;
logic [`XLEN-1:0] PCTargetE;
@ -84,7 +84,7 @@ module wallypipelinedhart (
logic PCSrcE;
logic CSRWritePendingDEM;
logic LoadStallD, MulDivStallD, CSRRdStallD;
logic DivDoneW;
logic DivDoneW;
logic [4:0] SetFflagsM;
logic [2:0] FRM_REGW;
logic FloatRegWriteW;
@ -132,15 +132,15 @@ module wallypipelinedhart (
.Funct7M(InstrM[31:25]),
.*);
pagetablewalker pagetablewalker(.*); // can send addresses to ahblite, send out pagetablestall
// *** can connect to hazard unit
// changing from this to the line above breaks the program. auipc at 104 fails; seems to be flushed.
// Would need to insertinstruction as InstrD, not InstrF
/*ahblite ebu(
.InstrReadF(1'b0),
.InstrRData(), // hook up InstrF later
.MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]),
.*); */
pagetablewalker pagetablewalker(.*); // can send addresses to ahblite, send out pagetablestall
// *** can connect to hazard unit
// changing from this to the line above breaks the program. auipc at 104 fails; seems to be flushed.
// Would need to insertinstruction as InstrD, not InstrF
/*ahblite ebu(
.InstrReadF(1'b0),
.InstrRData(), // hook up InstrF later
.MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]),
.*); */
muldiv mdu(.*); // multiply and divide unit