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https://github.com/openhwgroup/cvw
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The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables.
This commit is contained in:
Ross Thompson
parent
67881ff686
commit
8486f426b7
170
wally-pipelined/src/ifu/bpred.sv
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170
wally-pipelined/src/ifu/bpred.sv
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///////////////////////////////////////////
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// bpred.sv
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//
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// Written: Ross Thomposn
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// Email: ross1728@gmail.com
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// Created: February 12, 2021
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// Modified:
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//
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// Purpose: Branch prediction unit
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// Produces a branch prediction based on branch history.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module bpred
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(input logic clk, reset,
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input logic StallF, StallD, StallE, FlushF, FlushD, FlushE,
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// Fetch stage
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// the prediction
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input [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list
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output [`XLEN-1:0] BPPredPCF,
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output SelBPPredF,
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input [31:0] InstrF, // we are going to use the opcode to indicate what type instruction this is.
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// if this is too slow we will have to predict the type of instruction.
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// Execute state
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// Update Predictor
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input [`XLEN-1:0] PCE, // The address of the currently executing instruction
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// 1 hot encoding
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// return, jump register, jump, branch
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// *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class.
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// *** the specifics of how this is encode is subject to change.
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input PCSrcE, // AKA Branch Taken
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// Signals required to check the branch prediction accuracy.
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input [`XLEN-1:0] PCTargetE, // The branch destination if the branch is taken.
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input [`XLEN-1:0] PCD, // The address the branch predictor took.
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input [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
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// Report branch prediction status
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output BPPredWrongE
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);
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logic BTBValidF;
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logic [1:0] BPPredF, BPPredD, BPPredE, UpdateBPPredE;
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logic [3:0] InstrClassD, InstrClassF, InstrClassE;
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logic [`XLEN-1:0] BTBPredPCF, RASPCF;
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logic TargetWrongE;
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logic FallThroughWrongE;
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logic PredictionDirWrongE;
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logic PredictionPCWrongE;
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// Part 1 decode the instruction class.
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// *** for now I'm skiping the compressed instructions
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assign InstrClassF[3] = InstrF[5:0] == 7'h67 && InstrF[19:15] == 5'h01; // return
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// This is probably too much logic.
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// *** This also encourages me to switch to predicting the class.
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assign InstrClassF[2] = InstrF[5:0] == 7'h67 && InstrF[19:15] == 5'h01; // jump register, but not return
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assign InstrClassF[1] = InstrF[5:0] == 7'h6F; // jump
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assign InstrClassF[0] = InstrF[5:0] == 7'h63; // branch
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// Part 2 branch direction prediction
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twoBitPredictor predictor(.LookUpPC(PCNextF),
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.Prediction(BPPredF),
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// update
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.UpdatePC(PCE),
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.UpdateEN(InstrClassE[0]),
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.UpdatePrediction(UpdateBPPredE));
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// this predictor will have two pieces of data,
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// 1) A direction (1 = Taken, 0 = Not Taken)
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// 2) Any information which is necessary for the predictor to built it's next state.
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// For a 2 bit table this is the prediction count.
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assign SelBPPredF = ((InstrClassF[0] & BPPredF[1]) |
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InstrClassF[3] |
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(InstrClassF[2]) |
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InstrClassF[1]) & BTBValidF;
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// Part 3 Branch target address prediction
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// *** For now the BTB will house the direct and indirect targets
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BTBPredictor targetPredictor(.LookUpPC(PCNextF),
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.TargetPC(BTBPredPCF),
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.Valid(BTBValidF),
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// update
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.UpdateEN(InstrClassE[2] | InstrClassE[1] | InstrClassE[0]),
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.UpdatePC(PCE),
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.UpdateTarget(PCTargetE));
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// Part 4 RAS
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RASPredictor RASPredictor(.pop(InstrClassF[3]),
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.popPC(RASPCF),
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.push(InstrClassE[3]),
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.pushPC(PCLinkE));
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assign BPPredPCF = InstrClassF[3] ? RASPCF : BTBPredPCF;
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// The prediction and its results need to be passed through the pipeline
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// *** for other predictors will will be different.
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flopenrc #(2) BPPredRegD(.clk(clk),
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.reset(reset),
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.en(~StallF),
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.clear(FlushF),
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.d(BPPredF),
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.Q(BPPredD));
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flopenrc #(2) BPPredRegE(.clk(clk),
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.reset(reset),
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.en(~StallD),
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.clear(FlushD),
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.d(BPPredD),
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.Q(BPPredE));
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// pipeline the class
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flopenrc #(4) InstrClassRegD(.clk(clk),
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.reset(reset),
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.en(~StallF),
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.clear(FlushF),
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.d(InstrClassF),
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.q(InstrClassD));
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flopenr #(4) InstrClassRegE(.clk(clk),
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.reset(reset),
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.en(~StallD),
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.clear(flushD),
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.d(InstrClassD),
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.q(InstrClassE));
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// Check the prediction makes execution.
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assign TargetWrongE = PCTargetE != PCD;
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assign FallThroughWrongE = PCLinkE != PCD;
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assign PredictionDirWrongE = BPPredE ^ PCSrcE;
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assign PredictionPCWrongE = PCSrcE ? TargetWrongE : FallThroughWrongE;
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assign BPPredWrongE = PredictionPCWrongE | PredictionDirWrongE;
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// Update predictors
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satCounter2 BPDirUpdate(.BrDir(~PredictionDirWrongE),
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.OldState(BPPredE),
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.NewState(UpdateBPPredE));
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58
wally-pipelined/src/ifu/satCounter2.sv
Normal file
58
wally-pipelined/src/ifu/satCounter2.sv
Normal file
@ -0,0 +1,58 @@
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///////////////////////////////////////////
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// satCounter2.sv
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//
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// Written: Ross Thomposn
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// Email: ross1728@gmail.com
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// Created: February 13, 2021
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// Modified:
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//
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// Purpose: 2 bit starting counter
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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||||
//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module satCounter2
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(input logic BrDir,
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input logic Decr,
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input logic [1:0] OldState,
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output logic [1:0] NewState
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);
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always_comb begin
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case(OldState)
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2'b00: begin
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if(BrDir) NewState = 2'b01;
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else NewState = 2'b00;
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end
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2'b01: begin
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if(BrDir) NewState = 2'b10;
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else NewState = 2'b00;
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end
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2'b10: begin
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if(BrDir) NewState = 2'b11;
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else NewState = 2'b01;
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end
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2'b11: begin
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if(BrDir) NewState = 2'b11;
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else NewState = 2'b10;
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end
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endcase
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end
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endmodule
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