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Debugging bus interface.
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@ -110,6 +110,7 @@ module ahblite (
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if (MemReadM) NextAdrState = MEMREAD;
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else if (MemWriteM) NextAdrState = MEMWRITE;
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else if (InstrReadF) NextAdrState = INSTRREAD;
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// else if (1) NextAdrState = INSTRREAD; // dm 2/9/2021 testing
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else NextAdrState = IDLE;
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// Generate acknowledges based on bus state and ready
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@ -159,8 +160,10 @@ module ahblite (
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else InstrState <= NextInstrState;*/
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assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM && InstrReadF)) ||
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(InstrState == 1 && ~InstrAckD) ||
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(InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing
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(InstrState == 1 && ~InstrAckD) ||
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(InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing; delete this later
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/* assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM)) ||
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(InstrState == 1 && ~InstrAckD); // *** removed InstrReadF above dh 2/9/20 */
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assign InstrStall = NextInstrState | MemState | NextMemState; // *** check this, explain better
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// temporarily turn off stalls and check it works
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//assign DataStall = 0;
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@ -61,7 +61,7 @@ module hazard(
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assign StallDCause = LoadStallD; // stall in decode if instruction is a load dependent on previous
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assign StallECause = 0;
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assign StallMCause = 0; // sDataStall; // not yet used***
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assign StallWCause = DataStall;
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assign StallWCause = DataStall; // | InstrStall;
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// Each stage stalls if the next stage is stalled or there is a cause to stall this stage.
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assign StallF = StallD | StallFCause;
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@ -75,6 +75,7 @@ string tests64iNOc[] = {
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"rv64i/I-MISALIGN_JMP-01","2000"
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};
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string tests64i[] = '{
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"rv64i/I-ENDIANESS-01", "2010",
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"rv64i/I-ADD-01", "3000",
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"rv64i/I-ADDI-01", "3000",
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"rv64i/I-ADDIW-01", "3000",
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