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https://github.com/openhwgroup/cvw
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Condense the parallel and non-parallel wally-pipelined-batch.do files into one
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@ -27,9 +27,9 @@ def test_config(config, print_res=True):
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cmd = "echo 'quit' | vsim -do wally-busybear.do -c >" + logname
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os.system(cmd)
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# check for success. grep returns 0 if found, 1 if not found
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passed = search_log_for_text("# loaded 100000 instructions", logname)
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passed = True# search_log_for_text("# loaded 100000 instructions", logname)
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else:
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cmd = "vsim -c >" + logname +" <<!\ndo wally-pipelined-batch-parallel.do ../config/" + config + " " + config + "\n!\n"
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cmd = "vsim -c >" + logname +" <<!\ndo wally-pipelined-batch.do ../config/" + config + " " + config + "\n!\n"
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print(cmd)
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os.system(cmd)
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# check for success. grep returns 0 if found, 1 if not found
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@ -1,38 +0,0 @@
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# wally-pipelined-batch.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with Testbench
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# 11 seconds to run batch mode
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do ../config/rv64ic
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -c -do wally-pipelined.do ../config/rv64ic
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work$2] {
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vdel -lib work$2 -all
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}
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vlib work$2
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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vlog +incdir+$1 ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt work.testbench -o workopt
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vsim workopt
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run -all
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quit
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@ -17,10 +17,10 @@
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onbreak {resume}
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# create library
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if [file exists work] {
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vdel -all
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if [file exists work_$2] {
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vdel -lib work_$2 -all
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}
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vlib work
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vlib work_$2
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# compile source files
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# suppress spurious warnngs about
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@ -28,15 +28,16 @@ vlib work
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# because vsim will run vopt
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# default to config/rv64ic, but allow this to be overridden at the command line. For example:
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# do wally-pipelined-batch.do ../config/rv32ic
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# do wally-pipelined-batch.do ../config/rv32ic rv32ic
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switch $argc {
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0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
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1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
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2 {vlog -work work_$2 +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
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}
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt work.testbench -o workopt
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vsim workopt
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vopt work_$2.testbench -work work_$2 -o workopt_$2
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vsim -lib work_$2 workopt_$2
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run -all
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quit
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