Noah Boorstin cdcacb8dbe change how testbench reads data ... we're not sure if this is a good idea, but for now, we broke things up into 3 seperate files, each read seperately. One for pc and instructions, one for registers, and one for memory reads. Each is scrolled through essentially independantly: new pc data is read and checked whenever pc changes, new register data is checked whenever any register changes, and a new mem read value is gotten whenever DataAdrM or MemRWM changes and MemRWM is not zero. I'm not super sure about the last one. Currently it looks like things should be working, but it goes wrong after, like, 3 instructions.		2021-01-22 20:27:01 -05:00
..
bin	cleanup	2021-01-18 00:42:40 -05:00
src	change how testbench reads data	2021-01-22 20:27:01 -05:00
testgen	testgen-ADD-SUB working and testbench simualtes with new vectors for rv32 and rv64	2021-01-20 01:04:28 -05:00
lint-wally	Sped up exe2memfile.pl	2021-01-17 18:45:19 -05:00
sim-wally	Initial Checkin	2021-01-14 23:37:51 -05:00
sim-wally-batch	Initial Checkin	2021-01-14 23:37:51 -05:00
wally-busybear.do	Start adding register checking	2021-01-22 15:11:13 -05:00
wally-pipelined-batch.do	Initial Checkin	2021-01-14 23:37:51 -05:00
wally-pipelined.do	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
wally.old	Initial Checkin	2021-01-14 23:37:51 -05:00