Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-23 13:04:28 +00:00
Code Issues Packages Projects Releases Wiki Activity

change regfile to not hold state of x0

Browse Source
This commit is contained in:
Noah Boorstin 2021-01-22 15:11:55 -05:00
parent 5b0070ac0b
commit adfeb29b77
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
wally-pipelined/src/regfile.sv
View File

@ -32,7 +32,7 @@ module regfile #(parameter XLEN=32) (
input logic [XLEN-1:0] wd3,
output logic [XLEN-1:0] rd1, rd2);
logic [XLEN-1:0] rf[31:0];
logic [XLEN-1:0] rf[31:1];
integer i;
// three ported register file
@ -45,7 +45,7 @@ module regfile #(parameter XLEN=32) (
always_ff @(negedge clk or posedge reset)
if (reset) for(i=0; i<32; i++) rf[i] <= 0;
else if (we3) rf[a3] <= wd3;
else if (we3 & (a3 != 0)) rf[a3] <= wd3;
assign #2 rd1 = (a1 != 0) ? rf[a1] : 0;
assign #2 rd2 = (a2 != 0) ? rf[a2] : 0;