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https://github.com/openhwgroup/cvw
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Updates to WALLY-IE tests
This commit is contained in:
ushakya22
parent
d6949b5b81
commit
0dfeb76f10
@ -3,6 +3,7 @@
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# testgen-IE.py
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#
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# ushakya@hmc.edu 31 March 2021
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# Modified: 4 April 2021
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#
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# Generate directed and random test vectors for RISC-V Design Validation.
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##################################
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@ -21,67 +22,212 @@ from random import getrandbits
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def writeTrapHandlers(storecmd):
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global testnum
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reg1 = 30
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reg2 = 29
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reg3 = 28
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lines = "\n# Trap Handler: Timer Interupt\n"
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lines += "_timer_trap_handler:\n"
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[reg1, reg2, reg3] = [30, 29, 28]
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[reg4, reg5] = [27, 26]
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lines = "\n# Trap Handler: Machine Timer Interupt\n"
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lines += "_timerM_trap_handler:\n"
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lines += "li x" + str(reg1) + ", MASK_XLEN(0x2A)\n"
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lines += str(storecmd) + " x" + str(reg1) + ", " + str(wordsize*testnum) + "(x6)\n"
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lines += "la x" + str(reg2) + ", 0x2004000\n"
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lines += str(storecmd) + " x" + str(reg1) + ", 0(x" + str(reg2) + ")\n"
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lines += "csrrw x" + str(reg3) + ", mepc, x0\n"
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lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: Supervisor Timer Interupt\n"
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lines += "_timerS_trap_handler:\n"
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lines += "li x" + str(reg4) + ", MASK_XLEN(0x20)\n"
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lines += "csrrc x0, mip, x" + str(reg4) + "\n"
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lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
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lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: User Timer Interupt\n"
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lines += "_timerU_trap_handler:\n"
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lines += "li x" + str(reg4) + ", MASK_XLEN(0x10)\n"
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lines += "csrrc x0, mip, x" + str(reg4) + "\n"
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lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
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lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: Machine Software Interupt\n"
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lines += "_softwareM_trap_handler:\n"
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lines += "li x" + str(reg1) + ", MASK_XLEN(0x0)\n" # clear MSIP bit in CLINT
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lines += "la x" + str(reg2) + ", 0x2000000\n"
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lines += str(storecmd) + " x" + str(reg1) + ", 0(x" + str(reg2) + ")\n"
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lines += "csrrw x" + str(reg3) + ", mepc, x0\n"
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lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: Supervisor Software Interupt\n"
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lines += "_softwareS_trap_handler:\n"
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lines += "li x" + str(reg4) + ", MASK_XLEN(0x2)\n"
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lines += "csrrc x0, mip, x" + str(reg4) + "\n"
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lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
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lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: User Software Interupt\n"
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lines += "_softwareU_trap_handler:\n"
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lines += "li x" + str(reg4) + ", MASK_XLEN(0x1)\n"
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lines += "csrrc x0, mip, x" + str(reg4) + "\n"
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lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
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lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: Machine External Interupt\n"
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lines += "_externalM_trap_handler:\n"
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#lines += "li x" + str(reg1) + ", MASK_XLEN(0x0)\n" # clear MSIP bit in CLINT
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#lines += "la x" + str(reg2) + ", 0x2000000\n"
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#lines += str(storecmd) + " x" + str(reg1) + ", 0(x" + str(reg2) + ")\n"
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lines += "csrrw x" + str(reg3) + ", mepc, x0\n"
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lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: Supervisor External Interupt\n"
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lines += "_externalS_trap_handler:\n"
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lines += "li x" + str(reg4) + ", MASK_XLEN(0x200)\n"
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lines += "csrrc x0, mip, x" + str(reg4) + "\n"
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lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
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lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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lines += "\n# Trap Handler: User External Interupt\n"
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lines += "_externalU_trap_handler:\n"
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lines += "li x" + str(reg4) + ", MASK_XLEN(0x100)\n"
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lines += "csrrc x0, mip, x" + str(reg4) + "\n"
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lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
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lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
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lines += "mret\n"
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f.write(lines)
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def writeVector(a, xlen, storecmd):
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def getInteruptEnableValues():
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if test == "timerM":
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mstatusE = 0x8
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mieE = 0x80
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elif test == "timerS":
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mstatusE = 0x2
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mieE = 0x20
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elif test == "timerU":
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mstatusE = 0x1
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mieE = 0x10
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elif test == "softwareM":
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mstatusE = 0x8
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mieE = 0x8
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elif test == "softwareS":
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mstatusE = 0x2
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mieE = 0x2
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elif test == "softwareU":
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mstatusE = 0x1
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mieE = 0x1
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elif test == "externalM":
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mstatusE = 0x8
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mieE = 0x800
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elif test == "externalS":
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mstatusE = 0x2
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mieE = 0x200
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elif test == "externalU":
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mstatusE = 0x1
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mieE = 0x100
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return [mstatusE, mieE]
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def getMcause():
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b = 1 << (xlen-1)
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if test == "timerM":
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b = b + 0x7
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elif test == "timerS":
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b = b + 0x5
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elif test == "timerU":
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b = b + 0x4
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elif test == "softwareM":
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b = b + 0x3
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elif test == "softwareS":
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b = b + 0x1
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elif test == "softwareU":
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b = b
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elif test == "externalM":
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b = b + 0xB
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elif test == "externalS":
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b = b + 0x9
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elif test == "externalU":
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b = b + 0x8
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return b
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def writeVectors(a, xlen, storecmd):
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global testnum
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[reg1, reg2, reg3] = [1, 2, 3]
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[reg5, reg8] = [5, 8]
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[reg9, reg10, reg11, reg12] = [9, 10, 11, 12]
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lines = "\n# Testcase 0: Timer Interupt\n"
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# Page 6 of unpriviledged spec
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# For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects
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lines = f"\n# Testcase {testnum}: {test} Interupt\n"
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# mcause code
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b = 1 << (xlen-1)
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b = b + 0x7
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expected = b
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lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
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expected = getMcause()
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lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(expected) + ")\n"
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if (testnum == 0): expected = 0
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[mstatusE, mieE] = getInteruptEnableValues()
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# set interupt enable bit in mstatus
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x8)\n"
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lines += "li x" + str(reg3) + ", MASK_XLEN(" + str(mstatusE) + ")\n"
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lines += "csrrs x0, mstatus, x" + str(reg3) + "\n"
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# set machine timer interupt enable bit in mie
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lines += "li x" + str(reg9) + ", MASK_XLEN(0x80)\n"
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# set timer interupt enable bit in mie
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lines += "li x" + str(reg9) + ", MASK_XLEN(" + str(mieE) + ")\n"
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lines += "csrrs x0, mie, x" + str(reg3) + "\n"
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# Save and set trap handler address for machine mode timer interrupt
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lines += "la x" + str(reg5) + ", _timer_trap_handler\n"
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# Save and set trap handler address for interrupt
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lines += "la x" + str(reg5) + ", _" + test + "_trap_handler\n"
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# save orignal mtvec address
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lines += "csrrw x" + str(reg12) + ", mtvec, x" + str(reg5) + "\n"
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# cause timer interupt
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#if (testnum == 0):
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lines += "li x" + str(reg8) + ", MASK_XLEN(0)\n"
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lines += str(storecmd) + " x" + str(reg8) + ", " + str(wordsize*testnum)+ "(x6)\n"
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if test == "timerM":
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lines += "li x" + str(reg8) + ", MASK_XLEN(0)\n"
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lines += str(storecmd) + " x" + str(reg8) + ", " + str(wordsize*testnum)+ "(x6)\n"
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lines += "la x" + str(reg8) + ", 0x2004000\n"
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lines += "li x" + str(reg3) + ", MASK_XLEN(0)\n"
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# save old value of mtimecmp and then set mtimecmp to zero
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lines += "lw x" + str(reg11) + ", 0(x" + str(reg8) + ")\n"
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lines += str(storecmd) + " x" + str(reg3) + ", 0(x" + str(reg8) + ")\n"
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elif test == "timerS":
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x20)\n"
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lines += "csrrs x0, mip, x" + str(reg3) + "\n"
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elif test == "timerU":
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x10)\n"
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lines += "csrrs x0, mip, x" + str(reg3) + "\n"
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lines += "la x" + str(reg8) + ", 0x2004000\n"
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# cause software interupt
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if test == "softwareM":
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lines += "la x" + str(reg8) + ", 0x2000000\n" # Write to the MSIP bit in CLINT
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x1)\n"
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lines += str(storecmd) + " x" + str(reg3) + ", 0(x" + str(reg8) + ")\n"
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elif test == "softwareS":
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x2)\n"
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lines += "csrrs x0, mip, x" + str(reg3) + "\n"
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elif test == "softwareU":
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x1)\n"
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lines += "csrrs x0, mip, x" + str(reg3) + "\n"
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# cause external interupt
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# Not sure how to cause an external machine interupt yet
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# will writing to PLIC just cause it? (where is the ExtIntM located in PLIC)
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#if test == "externalM":
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#lines += "la x" + str(reg8) + ", 0x2000000\n" # Write to the MSIP bit in CLINT
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#lines += "li x" + str(reg3) + ", MASK_XLEN(0x1)\n"
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#lines += str(storecmd) + " x" + str(reg3) + ", 0(x" + str(reg8) + ")\n"
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if test == "externalS":
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x200)\n"
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lines += "csrrs x0, mip, x" + str(reg3) + "\n"
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elif test == "externalU":
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lines += "li x" + str(reg3) + ", MASK_XLEN(0x100)\n"
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lines += "csrrs x0, mip, x" + str(reg3) + "\n"
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lines += "li x" + str(reg3) + ", MASK_XLEN(0)\n"
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# save old value of mtimecmp and then set mtimecmp to zero
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lines += "lw x" + str(reg11) + ", 0(x" + str(reg8) + ")\n"
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lines += str(storecmd) + " x" + str(reg3) + ", 0(x" + str(reg8) + ")\n"
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#lines += "wfi\n" # wait for interupt to be taken
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lines += "nop\nnop\n"
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@ -105,7 +251,7 @@ def writeVector(a, xlen, storecmd):
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##################################
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# change these to suite your tests
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tests = ["timer"]
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tests = ["timerM", "timerS", "timerU", "softwareM", "softwareS", "softwareU"]
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author = "ushakya@hmc.edu"
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xlens = [64, 32]
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numrand = 100;
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@ -149,8 +295,7 @@ for xlen in xlens:
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# print directed and random test vectors
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for i in range(0,numrand):
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a = getrandbits(xlen)
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b = getrandbits(xlen)
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writeVector(a, xlen, storecmd)
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writeVectors(a, xlen, storecmd)
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writeTrapHandlers(storecmd)
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@ -165,231 +310,3 @@ for xlen in xlens:
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f.write(lines)
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f.close()
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r.close()
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"""
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#!/usr/bin/python3
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##################################
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# testgen-IE.py
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#
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# ushakya@hmc.edu 24 Mar 2021
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#
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# Generate tests for mie CSR for RISC-V Design Validation.
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##################################
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##################################
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# libraries
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##################################
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from datetime import datetime
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from random import randint
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from random import seed
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from enum import Enum
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from random import getrandbits
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##################################
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# functions
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##################################
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def randRegs():
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reg1 = randint(1,30)
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reg2 = randint(1,30)
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reg3 = randint(1,30)
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if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
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return randRegs()
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else:
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return reg1, reg2, reg3
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def writeVectors(storecmd):
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global testnum
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reg1, reg2, reg3 = randRegs()
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# Set interupt enable bit in mstatus
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lines = ""
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li x2, 0x8
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csrrs x3, mstatus, x2
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""
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f.write(lines)
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# Save and set trap handler address for machine mode timer interrupt
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lines += ""
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la x1, _timer_trap_handler
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csrrw x31, mtvec, x1
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""
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f.write(lines)
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# Machine Mode Timer Interrupt (when interupt is enabled)
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# is this not working because mtimecmp isn't implemented????
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write(f""
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li x2, 0x0
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li x4, 0x80
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csrrs x0, mie, x4
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{storecmd} x2, {str(wordsize*testnum)}(x6)
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la x2, 0x2004000
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li x3, 0x0
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lw x5, 0(x2)
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sd x3, 0(x2)
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wfi
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"", storecmd, True, 4, "m")
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# Supervisor Timer Interrupt
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# user timer interupt
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# Machine mode external interrupt (hasn't been connected yet)
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# User external interrupt True, 8
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# Supervisor external interrupt True, 9
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# Save and set trap handler address for machine mode software interrupt
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# lines = ""
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# la x1, _interupt_trap_handler
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# csrrw x31, mtvec, x1
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# ""
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# f.write(lines)
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# Machine Mode software interupt (write to the CLINT)
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#write(f""
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# li x6, 0x0
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#
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# li x4, 0x8
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# csrrs x0, mie, x4
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#
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# li x3, 0x1
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# lw x4, clint
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# or x3, x4, x3
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# {storecmd} x3, clint
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# "", storecmd, True, 3, "m")
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# supervisor mode software interupt
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# user mode software interupt
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# timer interupt trap handler
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lines = f""
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_timer_trap_handler:
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li x2, 0x2A
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{storecmd} x2, {str(wordsize*testnum)}(x6)
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la x3, 0x2004000
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{storecmd} x2, 0(x3)
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mret
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""
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# software interupt trap handler
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#lines += f""
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#_interupt_trap_handler:
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#li x6, 0x2A
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#li x3, 0x0
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#lw x4, clint
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#xor x3, x4, x3
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#{storecmd} x3, 0(clint)
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#mret
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#""
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lines += storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)"
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f.write(lines)
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def write(lines, storecmd, interrupt, code, mode = "m"):
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global testnum
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# generate expected interrupt code
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expected = 0
|
||||
#(0 if not interrupt else (2**31 if xlen == 32 else 2**63)) + code
|
||||
# go back and fix expected
|
||||
|
||||
lines = f""
|
||||
# Testcase {testnum}
|
||||
li x31, 0
|
||||
{lines}
|
||||
|
||||
{storecmd} x31, {str(wordsize*testnum)}(x6)
|
||||
# RVTEST_IO_ASSERT_GPR_EQ(x0, 0, {formatstr.format(expected)})
|
||||
""
|
||||
|
||||
#if mode == "s":
|
||||
# go to supervisor mode
|
||||
#elif mode == "u":
|
||||
# go to user mode
|
||||
|
||||
f.write(lines)
|
||||
|
||||
if (xlen == 32):
|
||||
line = formatrefstr.format(expected)+""
|
||||
else:
|
||||
line = formatrefstr.format(expected % 2**32)+"" + formatrefstr.format(expected >> 32) + ""
|
||||
r.write(line)
|
||||
testnum = testnum+1
|
||||
|
||||
##################################
|
||||
# main body
|
||||
##################################
|
||||
|
||||
# name: (interrupt?, code)
|
||||
# tests = {
|
||||
# 'User software interrupt': (1, '0'),
|
||||
# 'Supervisor software interrupt': (1, '1'),
|
||||
# 'Machine software interrupt': (1, '3'),
|
||||
# 'User timer interrupt': (1, '4'),
|
||||
# 'Supervisor timer interrupt': (1, '5'),
|
||||
# 'Machine timer interrupt': (1, '7'),
|
||||
# 'User external interrupt': (1, '8'),
|
||||
# 'Supervisor external interrupt': (1, '9'),
|
||||
# 'Machine external interrupt': (1, '11'),
|
||||
# }
|
||||
author = "Udeema Shakya (ushakya@hmc.edu)"
|
||||
xlens = [64, 32]
|
||||
numrand = 60;
|
||||
|
||||
# setup
|
||||
seed(0xC395DDEB9173AD42) # make tests reproducible
|
||||
|
||||
# generate files for each test
|
||||
for xlen in xlens:
|
||||
formatstrlen = str(int(xlen/4))
|
||||
formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
|
||||
formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
|
||||
if (xlen == 32):
|
||||
storecmd = "sw"
|
||||
wordsize = 4
|
||||
else:
|
||||
storecmd = "sd"
|
||||
wordsize = 8
|
||||
|
||||
imperaspath = f"../../../imperas-riscv-tests/riscv-test-suite/rv{xlen}p/""
|
||||
basename = "WALLY-IE"
|
||||
fname = imperaspath + "src/" + basename + ".S"
|
||||
refname = imperaspath + "references/" + basename + ".reference_output"
|
||||
testnum = 0
|
||||
|
||||
# print custom header part
|
||||
f = open(fname, "w")
|
||||
r = open(refname, "w")
|
||||
line = "///////////////////////////////////////////"
|
||||
f.write(line)
|
||||
lines="// "+fname+ "// " + author + ""
|
||||
f.write(lines)
|
||||
line ="// Created " + str(datetime.now())
|
||||
f.write(line)
|
||||
|
||||
# insert generic header
|
||||
h = open("../testgen_header.S", "r")
|
||||
for line in h:
|
||||
f.write(line)
|
||||
|
||||
# print directed and random test vectors
|
||||
writeVectors(storecmd)
|
||||
|
||||
|
||||
# print footer
|
||||
h = open("../testgen_footer.S", "r")
|
||||
for line in h:
|
||||
f.write(line)
|
||||
|
||||
# Finish
|
||||
lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1"
|
||||
lines = lines + "RV_COMPLIANCE_DATA_END"
|
||||
f.write(lines)
|
||||
f.close()
|
||||
r.close()
|
||||
"""
|
||||
|
||||
Loading…
Reference in New Issue
Block a user