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1955 Commits

Author SHA1 Message Date
David Harris
acc9498ae2 Made SqrtE only true on square root so gating with ~MDUE can be removed) 2022-12-27 10:27:07 -08:00
David Harris
e34b8139af Check for non-negative W in int sign handling 2022-12-27 06:35:17 -08:00
Cedar Turek
f48b7d7ef9 fpu idiv working on all configs with 1 copy of radix 2! 2022-12-26 23:18:28 -08:00
Cedar Turek
0b14aa852d fpu passing idiv tests on rv32gc 1 copy of radix 2! 2022-12-26 21:47:56 -08:00
Cedar Turek
bebaf08bed took out otfc swap. updated postprocessing quotient/remainder logic for int div. 2022-12-26 21:03:56 -08:00
David Harris
c326a274ac Fixed early termination for square root 2022-12-26 08:54:57 -08:00
David Harris
2de66e9eef Moved fdivsqrtexpcalc to its own file 2022-12-26 08:45:43 -08:00
David Harris
a7204c9012 Removed unused DivSE from FPU 2022-12-26 07:29:19 -08:00
David Harris
fb0b2d4227 Moved floating-point tests earlier in Wally config 2022-12-25 22:31:20 -08:00
David Harris
7e77a39d32 Restored missing floating point load/store tests 2022-12-25 22:28:14 -08:00
David Harris
d627512d2b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-25 20:12:55 -08:00
Ross Thompson
4f436dc7f0 Added missing assignment for no branch predictor mode. 2022-12-24 17:08:29 -06:00
David Harris
0cc2b0fcd2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-24 12:24:38 -08:00
Ross Thompson
0d6ce1d459 Fixed bug with the performance counters not updating. 2022-12-24 14:24:17 -06:00
David Harris
10af4e4353 ALU cleanup 2022-12-24 07:18:35 -08:00
cturek
cc6f219bdd Added A Sign register. Fixed postprocessing logic for postinc and rem calculation. 2022-12-24 06:46:52 +00:00
Ross Thompson
b0d6c9616e Minor optimizations. 2022-12-23 20:11:36 -06:00
Ross Thompson
6e9d1eb180 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-23 19:51:23 -06:00
Katherine Parry
4b50ffac91 reworked negitive sticky bit handeling in fma 2022-12-23 17:01:34 -06:00
Ross Thompson
6f9e21d61b Improved comment. 2022-12-23 15:13:15 -06:00
Ross Thompson
a2de53aeeb Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
Ross Thompson
fe9361de34 Removed XEnE, YEnE, and ZEnE from forward logic. 
Cleanup comments.
 2022-12-23 14:27:03 -06:00
Ross Thompson
af9afafdae Cleanup floating point hazard logic. 2022-12-23 14:21:47 -06:00
Ross Thompson
b4c7998ded DON'T USE. First commit in attempt to move fpustall detection into the decode stage. 2022-12-23 12:47:18 -06:00
Ross Thompson
f6f66cb79e Removed ZForwardEnE and replaced with ZEnE. 
Similar for YForwardEnE.
 2022-12-23 12:27:51 -06:00
Ross Thompson
ca67e5588d Removed unnecessary stall when MatchDE was driven 1 by RdE == 0. 2022-12-23 11:45:42 -06:00
David Harris
f038494760 Commented out fdiv early termination - broke fsqrt test 2022-12-23 00:58:55 -08:00
David Harris
e061bacc9d Fixed early termination on fdivsqrt 2022-12-23 00:53:55 -08:00
David Harris
0505f1fd37 Moved InstrValidNotFLushed to csr including InstrValidM 2022-12-23 00:27:44 -08:00
David Harris
3b1fe78bdc Removed unused StallW from CSRs 2022-12-23 00:21:36 -08:00
David Harris
9e21358d75 Removed unused signals from FPU 2022-12-23 00:18:39 -08:00
David Harris
0a7ed944a5 Revert to 98b824 2022-12-22 23:58:14 -08:00
David Harris
56312cd0a6 Clean up unused FPU signals 2022-12-22 23:53:09 -08:00
David Harris
4d509f94ec FDIV merge 2022-12-22 23:03:03 -08:00
David Harris
2d72bed1f4 Removed unused signals in FPU and CSR 2022-12-22 22:59:05 -08:00
Ross Thompson
98b824c4c4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-22 22:51:33 -06:00
Ross Thompson
2cc4d66ded Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
Ross Thompson
03021765a6 The LSU is properly using FlushW rather than TrapM. 2022-12-22 21:47:34 -06:00
Ross Thompson
3b791b768a Success we've replaced TrapM with FlushD in the IFU. 2022-12-22 21:36:49 -06:00
Ross Thompson
e0e92952c3 Partial cleanup for BP. 2022-12-22 20:33:38 -06:00
Ross Thompson
206bc7daa6 Closing in on icache flushed by FlushD rather than TrapM. 2022-12-22 20:19:09 -06:00
Ross Thompson
b1475df5e1 Wavefile updates. 2022-12-22 19:45:02 -06:00
Kip Macsai-Goren
a768d70093 Added status.tvm bit test that passes make and regression 2022-12-22 14:43:22 -08:00
Ross Thompson
41fe876e7a First pass at resolving ifu flush on trap rather than FlushD. 2022-12-22 15:53:06 -06:00
David Harris
d4bedca1bf Code cleanup 2022-12-22 10:04:50 -08:00
cturek
ccbad67497 Added negative-result int diviison support in U and UM registers. 13 tests pass! 2022-12-22 16:25:37 +00:00
cturek
1b7ed72ece Moved swap from qslc to otfc 2022-12-22 15:44:50 +00:00
cturek
3574bedb08 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-22 05:45:00 +00:00
cturek
80ca75e216 Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc. 2022-12-22 05:44:55 +00:00
David Harris
c42967f5c6 XMerge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-21 20:39:38 -08:00
Ross Thompson
c8c73f47d2 CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled. 2022-12-21 22:13:05 -06:00
cturek
0b4d81bd4a worked out some bugs with int div cycles 2022-12-22 02:22:01 +00:00
cturek
c3fdc0ab23 Renamed signals to E and M stages, forwarded preprocessed n to fsm 2022-12-22 00:43:27 +00:00
Ross Thompson
84f8d9953f Updated cache fsm names to match book. 2022-12-21 16:49:53 -06:00
Ross Thompson
d72cf65809 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-21 16:13:09 -06:00
Ross Thompson
e7a44d8975 Changed GatedStallF to GatedStallD. 2022-12-21 16:12:55 -06:00
David Harris
d0a3e939e3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-21 14:12:25 -08:00
David Harris
8bc753a291 Added assertion about atomics needing caches 2022-12-21 13:57:28 -08:00
cturek
0c30ecf86d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-21 20:41:38 +00:00
David Harris
6d46261350 comment cleanup 2022-12-21 12:39:09 -08:00
David Harris
c7f3aae084 Only delegated bits of SIP are readable 2022-12-21 12:32:49 -08:00
cturek
ab71962dc0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-21 19:35:57 +00:00
cturek
c479b9f112 fixed normshift calculations 2022-12-21 19:35:47 +00:00
David Harris
5ef3a1d371 git push 
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
 2022-12-21 11:31:27 -08:00
David Harris
e327d70cdc Removed unused FPU signals 2022-12-21 11:31:22 -08:00
Ross Thompson
c3b43b2fac Waiting on fix for wally64periph uart test. 
would like to remove vectored interrupt adder.
 2022-12-21 13:16:09 -06:00
Ross Thompson
0b4186f1e8 Vectored interrupts now require 64 byte alignment. 
Eliminates adder.
 2022-12-21 12:05:49 -06:00
Ross Thompson
91f948a91c The optimzied PC+2/4 logic still hanges on wally32priv. 2022-12-21 09:19:34 -06:00
Ross Thompson
6858b7568c Renamed PCPlusUpperF to PCPlus4F. 2022-12-21 09:18:30 -06:00
Ross Thompson
3d95aa3423 Added timeout check to testbench. 
A watchdog checks the value of PCW.  If it does not change within 1M cycles immediately stop simulation and report an error.
 2022-12-21 09:18:00 -06:00
Ross Thompson
ac94b55e74 Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0. 
Switched to even simplier PC+2/4 logic.
 2022-12-21 09:00:09 -06:00
Ross Thompson
a02b40cf02 Changes to wave file. 2022-12-21 08:41:47 -06:00
Ross Thompson
fe723af1af Comments about PC+2/4. 2022-12-21 08:35:43 -06:00
David Harris
5d91b3044f Clean up vecgtored interrupts 2022-12-20 16:53:09 -08:00
David Harris
dd0a02f0c8 Converted tvecmux to structural 2022-12-20 16:24:04 -08:00
Ross Thompson
f860440361 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 18:09:37 -06:00
Ross Thompson
80be2e7be5 privileged pc mux cleanup. 2022-12-20 18:05:44 -06:00
Ross Thompson
97593e8a6f Moved privileged pc logic into privileged unit. 2022-12-20 17:55:45 -06:00
David Harris
8f640f050f IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI 2022-12-20 15:38:30 -08:00
Ross Thompson
35ad49502f Implement FENCE.I as NOP when ZIFENCEI is not supported. 2022-12-20 17:34:11 -06:00
Ross Thompson
0dc09ac22d Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 17:11:35 -06:00
Ross Thompson
65cbff9283 Changed long names of vectored pcm signals. 2022-12-20 17:01:20 -06:00
David Harris
f3e9950317 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-20 14:43:33 -08:00
David Harris
e7702e48b7 FPU remove unused signals 2022-12-20 14:43:30 -08:00
Ross Thompson
6f543d01b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 16:36:44 -06:00
Ross Thompson
8029b12f2a Renumbered bits for PCPlusUpper. 2022-12-20 16:33:49 -06:00
David Harris
caef1a6997 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-20 11:23:53 -08:00
David Harris
f0ef5caf32 Memory cleanup 2022-12-20 11:22:26 -08:00
Ross Thompson
c4901450c4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 12:58:59 -06:00
Ross Thompson
684d260005 Reorganized IFU PCNextF logic. 2022-12-20 12:58:54 -06:00
David Harris
e74d47bcb4 Renamed renamed sram to ram 2022-12-20 08:36:45 -08:00
David Harris
16f3c25cb7 sram1p1rw cleanup 2022-12-20 02:57:51 -08:00
David Harris
08234cb1c7 Remoed unused bram modules 2022-12-20 02:40:45 -08:00
David Harris
2c46f22be5 Renamed SRAM2P1R1W to lower case 2022-12-20 02:09:55 -08:00
David Harris
54e856c4f5 Renamed SRAM2P1R1W to lower case 2022-12-20 02:09:36 -08:00
David Harris
caf457106a Replaced || and && with single ops 2022-12-20 01:33:35 -08:00
Ross Thompson
dedc08bd42 several options for pcnextf on fence.i 2022-12-19 23:33:12 -06:00
Ross Thompson
2df18cc758 More bp/ifu pcmux cleanup. 2022-12-19 23:16:58 -06:00
Ross Thompson
565585b35a Moved more muxes inside bp. 2022-12-19 22:51:55 -06:00
Ross Thompson
d8ee0ea59d Begin cleanup of ifu. partial move of pc muxes inside bp. 2022-12-19 22:46:11 -06:00
David Harris
e4579f3e9b Removed CSR support from rv32i 2022-12-19 16:15:12 -08:00
David Harris
9fea16fd20 Simplified InstrRawD register 2022-12-19 15:18:42 -08:00
David Harris
a4da3f30e1 Explained hazard causes 2022-12-19 09:41:41 -08:00
David Harris
67763dbeec Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-19 09:09:57 -08:00
David Harris
3172dfd6a9 Properly decode fcvtint to prevent unnecessary stalls 2022-12-19 09:09:48 -08:00
Ross Thompson
159eda85f0 Renamed FStallD to FPUStallD. 2022-12-19 09:28:45 -06:00
Alessandro Maiuolo
5a82898649 Added NumZeroE, AZeroM, and BZeroM 2022-12-18 20:02:40 -08:00
Alessandro Maiuolo
2989782fe6 fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8) 2022-12-18 19:04:36 -08:00
Ross Thompson
4f56e6ff5d I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl. 2022-12-18 18:30:35 -06:00
Ross Thompson
376b01fcb8 Attempted to make a cache test. 2022-12-18 17:15:08 -06:00
Ross Thompson
ebdac1a9d0 Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
Ross Thompson
73fd3fe040 Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back. 2022-12-17 23:47:49 -06:00
Ross Thompson
cdeccd78e6 At long last found the subtle bug in the LRU. 
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
 2022-12-17 10:03:08 -06:00
Ross Thompson
ade06f3780 Fixed a bug with the new cache flush changes. 2022-12-16 19:28:32 -06:00
Ross Thompson
7d04675073 Cleanup comments. 2022-12-16 17:08:35 -06:00
Ross Thompson
89a30e7e37 Further cleanfsm cleanup. 2022-12-16 16:37:45 -06:00
Ross Thompson
9ebea891e2 More cachefsm cache flush cleanup. 2022-12-16 16:32:21 -06:00
Ross Thompson
731fbfc851 Oups found a bug with the new flush cache states. 2022-12-16 16:22:40 -06:00
Ross Thompson
41c636ecfa Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-16 15:37:03 -06:00
Ross Thompson
b462554896 Cleanup of cache flush fsm enhancement. 2022-12-16 15:36:53 -06:00
Ross Thompson
dacba855da Rough draft of cache flush fsm enhancement. 2022-12-16 15:28:22 -06:00
cturek
4b8cbd9fa0 Added integer support for initC 2022-12-16 19:02:11 +00:00
Ross Thompson
bc907f3e2f Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-16 12:52:22 -06:00
Ross Thompson
e425ecac96 Fixed regression-wally to correct remove and mkdir wkdir. 2022-12-16 12:51:21 -06:00
cturek
06c58f310d Added mux for integer special case, renamed signals to match pipelined stage 2022-12-16 18:43:49 +00:00
David Harris
378c40002f Clean up interrupt masking by Commit 2022-12-16 08:27:39 -08:00
David Harris
7989f449ad Disabled starting FPU divider when IDIV_ON_FPU = 0 2022-12-16 06:35:29 -08:00
cturek
d7571bb9b1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-16 03:41:39 +00:00
David Harris
b7abc0037e Use FlushE to reset integer divider FSM 2022-12-15 11:00:54 -08:00
David Harris
4365c99b52 Refactored stalls and flushes, including FDIV flush with FlushE 2022-12-15 10:56:18 -08:00
David Harris
5b040b7935 Regression delete wkdir files to prevent spurious failures 2022-12-15 10:24:58 -08:00
David Harris
2457448e29 Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE 2022-12-15 08:23:34 -08:00
Ross Thompson
fa19a111c6 Hazard cleanup. 2022-12-15 10:05:17 -06:00
Ross Thompson
e774dd2db9 Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage. 2022-12-15 09:53:35 -06:00
Ross Thompson
b02550b05c Merge branch 'main' into hazards 2022-12-15 08:44:59 -06:00
David Harris
33aca5d35e Added IDIV_ON_FPU flag to control whether integer division uses FPU 2022-12-15 06:37:55 -08:00
David Harris
5f637ef4a7 Use FPU divider for integer division when F is supported 2022-12-14 17:03:13 -08:00
cturek
8829e627eb Fixed BZero and initU/initUM muxes 2022-12-14 16:44:46 +00:00
Ross Thompson
09dcb56217 Signal renames to reflect figures. 2022-12-14 09:49:15 -06:00
Ross Thompson
a3ec829b80 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-14 09:34:34 -06:00
Ross Thompson
6da7849d27 Reduced complexity of linebytemask. 2022-12-14 09:34:29 -06:00
cturek
ed59736a4b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-14 15:13:44 +00:00
Ross Thompson
1ba1bed0b0 Broken dont' use. 2022-12-11 23:24:01 -06:00
Ross Thompson
0716aedbd5 Removed unused flushf. 2022-12-11 16:28:11 -06:00
Ross Thompson
115e9e7bb3 Renamed CPUBusy to GatedStallF in IFU. 2022-12-11 15:54:19 -06:00
Ross Thompson
ffc5bce0b6 Renamed CPUBusy in LSU. 2022-12-11 15:52:51 -06:00
Ross Thompson
c50a2bd8bf Changed CPUBusy to Stall in ebu modules. 2022-12-11 15:51:35 -06:00
Ross Thompson
3ddf509f28 Renamed CPUBusy to Stall in cache. 2022-12-11 15:49:34 -06:00
Ross Thompson
4aadd87679 Moved CPUBusy out of HPTW. 2022-12-11 15:48:00 -06:00
cturek
f57211bb49 Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs 2022-12-10 21:56:35 +00:00
Ross Thompson
d15cf5c65c Added comments about why it is not possible to use FlushWay and VictimWay directly. 2022-12-09 17:07:35 -06:00
Ross Thompson
1463e9b1d4 Finished merge of kip and ross's ifu fix. 2022-12-09 16:52:22 -06:00
Ross Thompson
6f01ea12e8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-09 16:42:16 -06:00
Ross Thompson
38adcb5b17 Minor simplification of cacheway way selection muxes. 2022-12-09 16:42:05 -06:00
Kip Macsai-Goren
f486a763d9 Addded fix for 32 bit periph test and added test to regression 2022-12-06 09:56:08 -08:00
Ross Thompson
033f844d09 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-06 10:38:14 -06:00
Ross Thompson
9ee2d84c7c Fixed bug Kip found. 
The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
 2022-12-06 10:37:45 -06:00
Kip Macsai-Goren
2dfa426e10 added passing GPIO test to 64 bit tests 2022-12-05 21:31:00 -08:00
Kip Macsai-Goren
c6c0ef05db commented out periph test from wally32 periph so rv32ic doesn't hang 2022-12-05 20:23:16 -08:00
Kip Macsai-Goren
ae32e2a9ee added passing tests to regression 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
282d06b45f added -01 to all WALLY tests 2022-12-05 20:16:02 -08:00
Ross Thompson
9806babe9e Renamed SelBusBuffer to SelFetchBuffer. 2022-12-05 17:51:13 -06:00
Ross Thompson
0fdbfb87eb Removed commented code. 2022-12-05 17:21:56 -06:00
Ross Thompson
bcb927d172 Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags. 2022-12-05 17:19:51 -06:00
Ross Thompson
2bcaacb179 Cache signal renames. 2022-12-04 16:09:09 -06:00
Ross Thompson
b84b709182 Optimized way selection logic. 2022-12-04 12:30:56 -06:00
Ross Thompson
74d5ccc2b1 Found possible optimization as the way selection is shared in cache, cacheway, and cachelru. 2022-12-04 01:20:51 -06:00
Ross Thompson
62e495c739 Moved selectedway mux into cacheway. It makes way more sense there. 2022-12-04 01:15:47 -06:00
Ross Thompson
e1ac736d43 Rename LineByteMux to FetchbufferbyteSel. 2022-12-04 01:00:04 -06:00
Ross Thompson
128b3d20e7 Updated riscv arch test removed misaligned1. 2022-12-04 00:18:10 +00:00
Ross Thompson
de99663b97 Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." 
This reverts commit 70b89e5214.
 2022-12-04 00:01:58 +00:00
cturek
70b89e5214 Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider. 2022-12-02 21:44:29 +00:00
cturek
1f32603c30 Added flops to preproc 2022-12-02 20:31:08 +00:00
David Harris
9395414df3 Renamed FPUStallD to FCvtIntStallD 2022-12-02 11:55:23 -08:00
David Harris
d64cd715f9 Renamed DivStartE to IFDivStartE 2022-12-02 11:30:49 -08:00
David Harris
9c1b7e53e4 FPU divider working with execute stage stall 2022-12-02 11:11:53 -08:00
David Harris
01028e7088 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-02 04:28:50 -08:00
David Harris
4c6003d9e2 update test list 2022-12-02 04:28:47 -08:00
Ross Thompson
33e4361de5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 22:36:07 -06:00
David Harris
8afc054e74 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 16:27:36 -08:00
David Harris
ed39099405 reorder tests 2022-12-01 16:27:33 -08:00
Ross Thompson
1d9b5badee Properly flush cacheLRU. 2022-12-01 17:32:58 -06:00
David Harris
f64c0589fe FPU test list 2022-12-01 10:18:36 -08:00
Ross Thompson
da92cdccd0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 11:47:54 -06:00
Ross Thompson
cb310bfb1d Removed unused port on cacheway. 2022-12-01 11:47:48 -06:00
David Harris
558f0b655e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-01 08:15:51 -08:00
David Harris
4e5f62a5c1 code cleanup 2022-12-01 08:15:48 -08:00
Ross Thompson
b0b16acaf5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-30 17:19:04 -06:00
David Harris
aa26a97b36 signal sufixes in integer division 2022-11-30 15:15:37 -08:00
Ross Thompson
f9ffcf377b Reverted the IROM/DTIM address range modelsim assignment. 2022-11-30 17:13:33 -06:00
Ross Thompson
bfd238a4fc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-30 13:30:37 -06:00
Ross Thompson
813b2963fb More optimization. 2022-11-30 11:26:48 -06:00
Ross Thompson
da7b13ba0a Removed reset on dirty cache bits. 2022-11-30 11:04:37 -06:00
Ross Thompson
5e5cca6ae1 Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now. 2022-11-30 11:01:25 -06:00
Ross Thompson
ac3e02692b Preparing to merge dirty and tag srams. 2022-11-30 10:40:48 -06:00
Ross Thompson
8692ccbafb Intermediate commit. Replaced flip flop dirty bit array with sram. 2022-11-30 00:08:31 -06:00
cturek
e28a6901a9 div tests in sim-wally 2022-11-30 02:32:04 +00:00
Ross Thompson
e3577781b0 Optimization of cacheway. 2022-11-29 18:30:47 -06:00
Ross Thompson
1e2180ef98 Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault. 2022-11-29 17:19:31 -06:00
Ross Thompson
5e550fe5e6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-29 14:57:38 -06:00
Ross Thompson
9e4166407b Fixed a bug with the replacement policy. It was updating the wrong set on load hits. 2022-11-29 14:51:09 -06:00
Ross Thompson
179d321683 Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled. 2022-11-29 14:09:48 -06:00
Kip Macsai-Goren
66fcb2bffe Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-29 10:43:44 -08:00
Kip Macsai-Goren
26b4147f40 added failing satp invalid tests to regression 2022-11-29 10:43:38 -08:00
Ross Thompson
ed54959378 Renamed signals in the cache. 2022-11-29 10:52:40 -06:00
Ross Thompson
4e52755c9f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-22 18:07:32 -06:00
cturek
7140642c93 Almost done with Int division 2022-11-22 22:22:59 +00:00
cturek
3fbccbf119 Updated testbench/wave for fdivsqrt new start signals 2022-11-22 22:22:26 +00:00
Ross Thompson
1736983557 Cleanup cacheLRU. 2022-11-22 14:59:01 -06:00
Ross Thompson
2ae7b555be File name change for cachereplacement policy to cacheLRU 2022-11-20 22:35:02 -06:00
Ross Thompson
84679c0062 Signal name changes for LRU. 2022-11-20 22:31:36 -06:00
Ross Thompson
736a30afac Missing a file. Last commit will fail. 2022-11-17 17:45:41 -06:00
Ross Thompson
a1f39a8186 Finally have the correct replacement policy implementation. 2022-11-17 17:36:37 -06:00
Ross Thompson
ac0f6ddb7b I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps. 2022-11-16 15:38:37 -06:00
Ross Thompson
9b2236b2a0 Progress on the cache replacement policy implementation. 2022-11-16 15:35:34 -06:00
Ross Thompson
cf964e30fb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-16 12:42:29 -06:00
Ross Thompson
5f7b0b8a9b Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr. 2022-11-16 12:36:58 -06:00
David Harris
bc3b783543 comment cleanup 2022-11-16 10:23:20 -08:00
David Harris
ddba68605e Renamed DivBusy to FDivBusyE in FPU 2022-11-16 10:13:27 -08:00
David Harris
e008d663f4 Moved DivStartE to fdivsqrtfsm 2022-11-16 10:00:07 -08:00
Ross Thompson
900a326a23 Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out. 2022-11-16 11:15:34 -06:00
cturek
6fe35ee0e3 Attempt to fix FPGA synth errors 2022-11-15 20:34:28 +00:00
cturek
1c49d4a1c2 Fixed lint errors in postprocessing 2022-11-15 20:31:23 +00:00
Ross Thompson
ec6517fadd Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state. 2022-11-14 16:02:20 -06:00
Ross Thompson
f03d5d3ac8 Renamed Flush to FlushStage in the cache. 2022-11-14 14:11:05 -06:00
Ross Thompson
1bf838fa6b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-14 13:48:56 -06:00
David Harris
895ee3d773 Removed comment about nonexistent possible bug 2022-11-14 09:56:33 -08:00
David Harris
cae3e00751 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-14 09:52:24 -08:00
David Harris
79d416537a Removed comment about nonexistent possible bug 2022-11-14 09:52:21 -08:00
Ross Thompson
1a00e7bbee Changed names of cache signals. 2022-11-13 21:36:12 -06:00
Ross Thompson
5800dfde60 Updated wave file. 2022-11-13 21:34:45 -06:00
cturek
0b2c8b9d46 Added majority of combinational logic 2022-11-14 00:06:38 +00:00
cturek
74f58b5d89 Added Quotient/Remainder calcs to normal termination 2022-11-13 23:44:34 +00:00
cturek
b3bfdbad18 Added flops for n and m, added B=0 signal 2022-11-13 23:02:43 +00:00
cturek
9c70ab917c Added A<B signal to fdivsqrt, started postprocessing merge 2022-11-13 22:40:26 +00:00
Ross Thompson
a27b81ef90 Changed IMWriteDataM to IHWriteDataM. 2022-11-13 12:27:48 -06:00
Ross Thompson
3ac6514856 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
hazard was not a straight forward merge.  I changed the way the LSU and IFU generate IFUStallF and LSUStallM.  They need to be suppressed by TrapM now.
 2022-11-13 12:25:22 -06:00
David Harris
0ce3cc393a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-13 04:23:26 -08:00
David Harris
157f816cd3 HPTW cleanup 2022-11-13 04:23:23 -08:00
David Harris
0502b8ea4d Comments about division hazards 2022-11-13 04:17:37 -08:00
Ross Thompson
90697ef888 Moved all remaining bus logic from the LSU into ahbcacheinterface. 2022-11-11 14:30:32 -06:00
cturek
ff410cd849 Added integer step counter to fsm 2022-11-11 00:23:25 +00:00
Ross Thompson
c2e3bad3f5 Fixed name change in hptw. 2022-11-10 16:13:31 -06:00
Ross Thompson
7311eca5ff Wavefile update. 2022-11-10 15:48:06 -06:00
Ross Thompson
64b818c49a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-10 15:46:25 -06:00
Ross Thompson
31d5eabd77 Renamed Word to Beat for ahbcacheinterface. 2022-11-09 17:52:50 -06:00
Ross Thompson
3653d6b3ed Renamed CACHE_EVICT to CACHE_WRITEBACK. 2022-11-09 17:43:06 -06:00
cturek
d5c5450f8d Reoredered tests for arch32m 2022-11-09 18:42:00 +00:00
cturek
e7c25f9562 Fixed asign and bsign 2022-11-09 18:41:26 +00:00
Ross Thompson
42c0a10d07 Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). 
FlushW prevents writting the cache, dtim, and bus state.  FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
 2022-11-07 15:50:55 -06:00