Ross Thompson 42c0a10d07 Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). ... FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS. FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to not stall W if we get a trap.		2022-11-07 15:50:55 -06:00
..
config	Added conditional OTFC swap for simplified int postprocessing	2022-11-06 23:09:09 +00:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.	2022-10-23 13:46:50 -05:00
src	Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).	2022-11-07 15:50:55 -06:00
testbench	Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.	2022-11-06 22:08:18 +00:00