Ross Thompson ac0f6ddb7b I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.		2022-11-16 15:38:37 -06:00
..
config	Added A<B signal to fdivsqrt, started postprocessing merge	2022-11-13 22:40:26 +00:00
misc
regression	Changed names of cache signals.	2022-11-13 21:36:12 -06:00
src	I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.	2022-11-16 15:38:37 -06:00
testbench	Reoredered tests for arch32m	2022-11-09 18:42:00 +00:00