Ross Thompson 5f7b0b8a9b Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.		2022-11-16 12:36:58 -06:00
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config	Added A<B signal to fdivsqrt, started postprocessing merge	2022-11-13 22:40:26 +00:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Changed names of cache signals.	2022-11-13 21:36:12 -06:00
src	Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.	2022-11-16 12:36:58 -06:00
testbench	Reoredered tests for arch32m	2022-11-09 18:42:00 +00:00