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1301 Commits

Author SHA1 Message Date
David Harris
171430a695 FPU and PMP tests 2024-01-21 14:41:22 -08:00
David Harris
ff055c404c fpu coverage improvements 2024-01-21 13:17:56 -08:00
David Harris
9d4a14b209 coverage improvements 2024-01-21 11:39:51 -08:00
David Harris
d801bf5d6c
Revert "more shiftcorrection bug fixes" 2024-01-21 10:41:14 -08:00
David Harris
9e6fa8076f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-01-21 10:15:38 -08:00
Kevin Kim
1459943a75 more shiftcorrection bug fixes 2024-01-21 10:08:48 -08:00
David Harris
69218b4b86 Coverage improvements 2024-01-21 10:03:07 -08:00
David Harris
17c9be7695 Cleanup typos, remove Zicond from riscof until it is working 2024-01-18 21:36:52 -08:00
David Harris
911b400af2 Fault on misaligned AMO 2024-01-18 13:13:56 -08:00
Rose Thompson
4c2ba2b0b4 Added StoreStall back to csrc. 2024-01-18 14:43:34 -06:00
Rose Thompson
81d006536a Lint passes with 32-bit no D$, but many regressions fail. 2024-01-18 09:48:44 -06:00
David Harris
d5e102d520 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-01-18 07:38:25 -08:00
Rose Thompson
ff6bb3be0c Fixed another bug with virtual memory and no caches. 2024-01-18 09:29:52 -06:00
Rose Thompson
e8474373e4 Fixed it so Virtual Memory work without a D$. 2024-01-18 09:18:17 -06:00
David Harris
74b242ce5c Partial implementation of fcvtmod.w.d; flags disagree in one case where Sail might be wrong, and result 134 is wrong because of overflow 2024-01-17 12:25:06 -08:00
Rose Thompson
2d3dc55986 Fixed bug. After I$ invalidated. If the pipelined wasn't stalled the I$ still output the old instruction on the next cycle. Now the I$ ensure that invalidation leads to the next cycle not hitting. 2024-01-17 12:19:10 -06:00
David Harris
4cfc86140c Zfa fmvh complete and passing tests: 2024-01-17 06:18:00 -08:00
David Harris
07e7e02241 Coded Zfa fmvp but no tests exist 2024-01-16 21:26:42 -08:00
David Harris
8654375f26 Zfa fminm/fmaxm/fltq/fleq implemented and tested 2024-01-16 20:03:54 -08:00
David Harris
9d57002c07 Zfa fli support working for F and D (add fli.sv module) 2024-01-16 17:27:59 -08:00
David Harris
0588d611ea Zfa fli support working for F and D 2024-01-16 17:27:40 -08:00
Rose Thompson
ed0f0d924b
Merge pull request #577 from davidharrishmc/dev 
Zfh fix and typo corrections
 2024-01-16 14:23:23 -06:00
David Harris
846a0c4d50 Check fma operations don't support H precision 2024-01-16 11:12:06 -08:00
David Harris
1a77c08f6e Fixed issues 575 and 477 about FPU tests failing when Zfh = 1. 2024-01-16 10:46:44 -08:00
David Harris
dcd40c6be7 Fixed spelling of output 2024-01-16 10:27:31 -08:00
David Harris
abecc98563 Fixed spelling of precision 2024-01-16 10:26:00 -08:00
Rose Thompson
ff5554ca61 Atomics work correctly without a d cache. 2024-01-16 10:43:20 -06:00
Rose Thompson
dfe5ef4427 Added logic for the non-cache atomics. 2024-01-15 17:47:17 -06:00
Rose Thompson
82a786f185 Hmm. Verilator is complaining about the parameter width. I'm not sure why so I changed to 1 bit. 2024-01-15 17:36:01 -06:00
Rose Thompson
614a83331f Fixed part of issue #405. 
The non-cache version of the bus controller did not have the correct supression of BusCommitted for a read only controller.
 2024-01-15 17:29:00 -06:00
Rose Thompson
83df3dfe83 Fixed the zifencei bug (part of issue 405). 2024-01-15 16:02:37 -06:00
David Harris
0235970313 Optimized away unused support for fmv with quads 2024-01-15 13:40:12 -08:00
David Harris
da4eca4854 Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int. 2024-01-15 13:24:57 -08:00
David Harris
9e78a7e290 Incorporated jstine fixes of FPU special case and testbench for conversion 2024-01-15 07:25:08 -08:00
David Harris
ed9fa07ba3 tests/coverage/tlbmisc.S 2024-01-15 07:16:11 -08:00
David Harris
fd181169fe Corrected spelling of negative 2024-01-15 07:15:23 -08:00
James E. Stine
b14cd67bef Values for IEEE 754 vs. RISC-V Table 11.4 in the RISC-V Unprivileged ISA 2024-01-14 22:08:42 -06:00
Jordan Carlin
51f670c821
Merge branch 'openhwgroup:main' into main 2024-01-12 19:43:01 -08:00
Rose Thompson
dd5f69cb78
Merge pull request #565 from davidharrishmc/dev 
Dev
 2024-01-12 21:30:27 -06:00
Jordan Carlin
092d10a3cd correct c.sext.b encoding and remove unreachable code in 01100 case 2024-01-12 19:09:10 -08:00
David Harris
d7b016e8f3 Cleaned up Zicond implementation 2024-01-12 18:12:52 -08:00
David Harris
6226c3db96
Revert "Fixes for Issue #541" 2024-01-12 07:50:13 -08:00
James E. Stine
e707eeb7c8 THis includes fix for special case when conversion from fp to int/long. The previous src did not test both the flags and result and so missed this subtle bug when an Invalid happens for this type of conversion. These results are indications of undefined behavior for these operations. All fp operations now passs when this update is fixed. Much of the information why these outputs should occur is somewhat alluded to by Pascal Cuoq originally from INSA in Lyon here: https://frama-c.com/2013/10/09/Overflow-float-integer.html 2024-01-12 00:37:50 -06:00
Rose Thompson
ceae2bc714
Merge pull request #561 from davidharrishmc/dev 
Added Zicond support
 2024-01-11 10:20:01 -06:00
David Harris
9eb6d9c8b8 Added Zicond support 2024-01-11 07:37:15 -08:00
Rose Thompson
a932bf6b66 Removed unnecessary spill for compressed aligned to end of cache line or uncached access. 2024-01-10 13:06:16 -06:00
Rose Thompson
588e1caeba Found bugs in the no I$ implementation's abhinterface width. We were only testing XLEN=32. XLEN=64 did not properly align instructions not aligned to 8 byte boundaries. 2024-01-06 22:29:16 -06:00
David Harris
67124b0c7f Fixed typo in declaration in tlbcontrol; escape quoted argument to Verilator; added ulimit to setup so Verilator stack is large enough 2024-01-06 07:11:25 -08:00
David Harris
0781cd4a44 Improved tlbcontrol to fault on R=0,W=1; fixed more coverage testsin tlbmisc.S; changed integer type to try to speed up CoreMark; comments in Verilate 2024-01-05 22:45:15 -08:00
Rose Thompson
1f3792c823 Fixed bug # 547, but there are other bugs which follow. 2024-01-05 23:32:10 -06:00
Rose Thompson
edc56c669e Fixed bug 546. non-leaf non-zero PBMT bit raise page fault. 2024-01-05 17:10:14 -06:00
David Harris
680a014876 Finished LSU tlbcontrol coverage tests 2024-01-02 10:16:20 -08:00
David Harris
d229dc06ee Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE 2024-01-02 00:35:17 -08:00
David Harris
f4ee05e1ea Coverage improvements 2024-01-01 08:31:09 -08:00
David Harris
e5ac2d5ef0 Modified align fsm to make coverage easier 2024-01-01 08:21:31 -08:00
David Harris
6181639003 Named IFU decomp generate block 2024-01-01 07:37:40 -08:00
David Harris
c52aef86a6 Fixed coverage exclusions that no longer reference code properly 2023-12-31 20:35:08 -08:00
David Harris
8795a9db7a Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-12-31 20:26:47 -08:00
David Harris
536539237c Fixed exclusion tags in pmachecker 2023-12-31 20:20:31 -08:00
Rose Thompson
626b89320c More cleanup. 2023-12-29 16:51:39 -06:00
Rose Thompson
730efefc41 Cleanup. 2023-12-29 16:18:30 -06:00
Rose Thompson
6a787981c2 Restored cache store delay hazard. 2023-12-29 16:10:27 -06:00
Rose Thompson
0264a17f77 Reverted dtim to use store delay stall, but only (load after store). 2023-12-29 16:06:30 -06:00
Rose Thompson
fbab9f6c6d Updated comments about AMO and CMO stalls. 2023-12-29 15:31:11 -06:00
Rose Thompson
f59fa5089d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-12-29 15:13:18 -06:00
Rose Thompson
8030b7d100 Added partial code for uncached amo operations. 
Minor fix for Makefile so coverage tests build.
 2023-12-29 15:07:20 -06:00
Rose Thompson
7afeee9807 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-12-29 14:49:36 -06:00
Jordan Carlin
2fa243c46e fixed coverage exclusions in lsu and ifu 2023-12-29 11:18:23 -08:00
Rose Thompson
52dad4f130 cbo.zero works for uncached memory now! 2023-12-29 11:11:06 -06:00
Rose Thompson
d1456b2471 Progress on fixing cbo.zero for uncached memory regions. 2023-12-29 11:03:38 -06:00
Rose Thompson
482529394a Fixed some of the uncached ifu bugs. 2023-12-29 09:53:22 -06:00
David Harris
2c2f692f3a Moved forwarding logic into controller 2023-12-26 21:17:01 -08:00
David Harris
e8df856fdb Renamed CMOp to CMOpM in mmu and cache 2023-12-25 05:57:41 -08:00
David Harris
6395cd0284 Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match 2023-12-21 12:29:37 -08:00
David Harris
06ddccd983 Fixed typo in IFU 2023-12-20 20:22:17 -08:00
David Harris
8eace30f49 Moved UnalignedPCNextF mux into IFU 2023-12-20 16:18:31 -08:00
David Harris
8552369687 Merged PR538, delete unused tests 2023-12-20 13:30:31 -08:00
Rose Thompson
b68dd74f89 Reverted logic to bit change. 2023-12-20 13:16:32 -06:00
Rose Thompson
18a96740d5 Revert RAM logic to bit change. 
Added logic to hptw to prevent x propagation.
 2023-12-20 13:10:20 -06:00
Rose Thompson
9de434a61b "Resolved" ram preload issues by replacing the RAM's types with bit from logic. Tested fpga synthesis. 2023-12-20 12:05:25 -06:00
Rose Thompson
9ee1ffe8fe Almost working with modelsim and verilator. 2023-12-20 11:29:31 -06:00
Rose Thompson
d617eb0977 DON'T keep this commit. 2023-12-19 16:56:40 -06:00
David Harris
b0f34a6377 Made priority of misalignment depend on ZICCLSM_SUPPORTED and made StoreAmo take prioirty over load faults 2023-12-19 12:51:45 -08:00
David Harris
6186181d46
Merge pull request #537 from ross144/main 
Almost having working Verilator.  One issue in the testbench remains.
 2023-12-18 18:13:56 -08:00
Rose Thompson
5062a8c89c Added parameter for cache's SRAM length. 
Progress towards verilator support.
 2023-12-18 12:50:49 -06:00
Rose Thompson
1d36ce3328 Fixed lint issue. 2023-12-18 12:03:54 -06:00
David Harris
6cb4a9e905 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-12-15 19:27:10 -08:00
David Harris
bbdcfe24ca
Merge pull request #533 from ross144/main 
Finally fixed the store delay hazard bug.
 2023-12-15 19:13:53 -08:00
Rose Thompson
438451ee02 Fixed the AMO hazard. 2023-12-15 11:55:54 -06:00
David Harris
51b43bffa3 ALU cleanup 2023-12-14 19:06:39 -08:00
David Harris
29f57958a9 Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match 2023-12-14 15:32:36 -08:00
David Harris
8eea2bdcc0
Merge pull request #531 from ross144/main 
Updated wavefile
 2023-12-14 14:52:31 -08:00
Rose Thompson
1ca9a8be6d I think I solved the AMO/store hazard issue introduced by removing the store delay hazard. 2023-12-14 16:31:02 -06:00
Rose Thompson
53bf68a585
Merge pull request #528 from davidharrishmc/dev 
Svnapot bug fix
 2023-12-13 21:30:47 -08:00
David Harris
166c98b6f6 Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn 2023-12-13 19:43:17 -08:00
Rose Thompson
a7f0aaa722 Added comments to finish store delay stall removal. 2023-12-13 20:35:13 -06:00
Rose Thompson
9cf6b1fdeb Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-12-13 20:34:35 -06:00
Rose Thompson
9f4c32d49c Merge branch 'main' of github.com:ross144/cvw 2023-12-13 20:32:59 -06:00
Rose Thompson
b69a5b59cd DTIM works without the store delay stall. Still a bit of work remaining. The DTIM needs cleanup. 
The cache needs a bit of clean up and the chapter needs updates.
The controller needs to be updated to remove the store delay hazard for cmo instructions.
 2023-12-13 20:32:14 -06:00
Rose Thompson
e089b421bb Got it working for the cache. 2023-12-13 20:24:46 -06:00
Rose Thompson
f592baa741 Closer. 2023-12-13 18:15:32 -06:00
Rose Thompson
eeced05f33 More progress towards store delay reduction. 2023-12-13 15:56:29 -06:00
Rose Thompson
f3d43a7713 Progress on reducing store stall in d cache. 2023-12-13 15:34:21 -06:00
David Harris
ff26baf7e8 Rolled back attempt to support Verilator 2023-12-13 12:53:44 -08:00
David Harris
333e390f8d Test commit from dev 2023-12-13 11:52:21 -08:00
David Harris
6c017141c5 Renamed HADE to ADUE for Svadu 2023-12-13 11:49:04 -08:00
David Harris
aff61ea97a Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator 2023-12-13 11:33:59 -08:00
Rose Thompson
3d0f9ce4f3 Cleaned up comments about pc reset. 2023-12-13 13:06:33 -06:00
Rose Thompson
c98c0dd3e0 Removed unnecessary pc reset logic from ifu and btb. 2023-12-13 13:05:10 -06:00
Rose Thompson
13bb5d845b On the way to solving the store delay hazard. 2023-12-13 10:39:01 -06:00
Jacob Pease
bc2c4d5295 Merge branch 'main' of github.com:openhwgroup/cvw 2023-12-04 15:23:22 -06:00
Rose Thompson
9348025727 Cachefsm simplifications. 2023-12-03 18:19:00 -06:00
Rose Thompson
1ebc7aa95a Optimized align. 2023-12-03 16:43:55 -06:00
Rose Thompson
3bef2a2361 Better name for cache signals. 2023-12-03 15:49:06 -06:00
Jacob Pease
7e494f2d3b Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile. 2023-12-01 18:59:18 -06:00
Rose Thompson
025b04ae8b Minior cleanup. 2023-11-29 19:44:59 -06:00
Rose Thompson
ab68a76e77 LineDirty is either the Victim Way or the Flush way dirty, but never the hitway dirty. CBO instructions require hitway dirty. However we cannot mux hitway dirty into LineDirty wihtout creating a combinational loop so we need a separate port. 2023-11-29 17:58:39 -06:00
Rose Thompson
f11f88ac2b Updates to tlb to check access permissions for cbo* 2023-11-29 16:20:43 -06:00
Rose Thompson
f4e4aac8b5 Added CMOp to pmp checker 2023-11-29 16:09:31 -06:00
Rose Thompson
fc04b6f7d8 Removed redundant ZICBOM/Z_SUPPORTED from pmachecker. 2023-11-29 15:39:39 -06:00
Rose Thompson
80336493f5 Cleaned up redundant ZICBOM/Z_SUPPORTED. 2023-11-29 15:20:49 -06:00
Rose Thompson
053b094620 Simpilified pmachecker for cmo. 2023-11-29 12:26:18 -06:00
Rose Thompson
d29b2b95f7 Additional cleanup. 2023-11-28 23:28:50 -06:00
Rose Thompson
4149ae6c11 More cleanup. 2023-11-28 23:05:47 -06:00
Rose Thompson
143c6ca4d1 Simplification to alignment. 2023-11-28 22:28:11 -06:00
Rose Thompson
a69a70ba7f Removed unused hardware from alignment. 2023-11-28 19:54:25 -06:00
Rose Thompson
865ebf8b9b cclsm cleanup. 2023-11-28 19:41:46 -06:00
Rose Thompson
f4e77e9669 Clean up. 2023-11-28 14:21:37 -06:00
Rose Thompson
df85428041 More optimizations for cclsm. 2023-11-28 14:19:30 -06:00
Rose Thompson
4d4790ecf9 Optimizations to cclsm. 2023-11-28 14:18:06 -06:00
Rose Thompson
0229df4a0f Oups. Introduced undetected bug into the cache's cbo insructions. 2023-11-28 01:03:48 -06:00
Rose Thompson
9a24a5d957 Renamed signal in pmachecker. 2023-11-28 00:05:12 -06:00
Rose Thompson
69653e5faa Fixed minor bug in the cbo hazard logic. 2023-11-27 23:38:53 -06:00
Rose Thompson
195def5808 Extended the abhcacheinterface to zero a cacheline's worth of uncached memory on cbo.zero. 2023-11-27 21:24:30 -06:00
Rose Thompson
9290c3f957 Added correct cbo fault behavior. 2023-11-27 20:57:33 -06:00
Rose Thompson
beb95dd592 Modified the pmachecker to correctly check the permissions for cmo instructions. 
However this isn't fully tested.
 2023-11-27 17:44:11 -06:00
Rose Thompson
337903d8dd More cache simplifications. 2023-11-27 14:59:42 -06:00
Rose Thompson
08549446ef Reduced cache fsm complexity. 2023-11-27 13:13:36 -06:00
Rose Thompson
c3da4c3c31 Clarified names in cacheway. 2023-11-27 12:56:11 -06:00
Rose Thompson
d7ef490c12 Sutble bug in the cacheway logic for cacheline invalidation. 2023-11-27 01:27:09 -06:00
David Harris
1f57df7f8b Fixed reference to deleted atomic signal in cache 2023-11-23 20:29:10 -08:00
David Harris
3f3c20a38f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-21 14:04:02 -08:00
David Harris
b5f79c44f9 Reset STIMECMP to 0 to agree with ImperasDV 2023-11-21 13:43:51 -08:00
Rose Thompson
58d89cc347 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-11-21 10:48:05 -06:00
Rose Thompson
386cf3eb56 Merge pull request #493 from stineje/main 
marchid approved by RISC-V
 2023-11-21 08:33:07 -08:00
James E. Stine
141cbd3f9f Update marchid/mvendorid for CV-Wally 2023-11-21 09:23:02 -06:00
David Harris
d3ce683e06 Removed other unused signals from Verilog 2023-11-20 23:37:56 -08:00
David Harris
f89fd8a7fe removed unused cache signals 2023-11-20 23:16:35 -08:00
Rose Thompson
1acc3951c8 More simplifications. 2023-11-21 00:19:24 -06:00
Rose Thompson
1d811b085c More cleanup. 2023-11-21 00:14:59 -06:00
Rose Thompson
d2a747bf3d cleanup. 2023-11-20 23:59:40 -06:00
Rose Thompson
70eb110a9c More optimizations to simplify cmo logic. 2023-11-20 22:13:31 -06:00
Rose Thompson
52ac07ce8d Removed the CMO_WRITEBACK state from the cache and unused signals. 2023-11-20 20:56:30 -06:00
Rose Thompson
667fe035c0 Simplified CMO.Zero fsm implementation slightly. 2023-11-20 17:01:43 -06:00
Rose Thompson
eed6f11df6 Merge branch 'main' of github.com:ross144/cvw 2023-11-20 11:29:45 -06:00
Rose Thompson
23e05cb8b2 Finally have the cbo way muxing controls reduced to something sane. 2023-11-20 11:28:03 -06:00
David Harris
8cb433cb66 Commented IROM preloading 2023-11-19 19:33:57 -08:00
David Harris
acd8a63628 Merge pull request #489 from ross144/main 
fixes issue #487
 2023-11-18 19:22:33 -08:00
Jacob Pease
a1e7158bd9 Merge branch 'main' of github.com:openhwgroup/cvw 2023-11-18 19:20:48 -06:00
Jacob Pease
87e6a5ccf2 Updated ROM to preload bootloader from file and infer a block ram when building for FPGA. 2023-11-18 19:15:39 -06:00
Rose Thompson
8cbd3de413 Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data. 2023-11-18 19:01:39 -06:00
David Harris
acc2db256f turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep 2023-11-17 20:25:24 -08:00
David Harris
eef39bd495 Fixed typo in lsu parameter 2023-11-15 08:30:48 -08:00
David Harris
817ddbc7c5 Adjusted LSU misaligned buffer to fix synthesis warning 2023-11-15 08:19:50 -08:00
David Harris
98176665de Fixed messed-up hazard.sv 2023-11-15 08:05:41 -08:00
naichewa
8ffce456bd Merge branch 'spi' into main 2023-11-14 14:51:06 -08:00
naichewa
1ab7c926ea Final Code Review 2023-11-14 13:44:59 -08:00
Rose Thompson
bf51948616 Merge pull request #474 from davidharrishmc/dev 
FP and synthesis cleanup
 2023-11-14 12:03:01 -08:00
David Harris
8ba0336c6f Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e 2023-11-14 11:01:58 -08:00
David Harris
a77bea9954 Merge pull request #472 from ross144/main 
Merge Zicclsm into main branch and removes the FPGA config.  FPGA makefile now automatically creates the config when building
 2023-11-14 08:34:06 -08:00
Rose Thompson
95fc5f4a1c Towards removing the FPGA config file. 2023-11-13 17:20:26 -06:00
Rose Thompson
a6995af91c Fixed bug in uncore updates which broke SDC. 2023-11-13 16:15:23 -06:00
Rose Thompson
707b0c557c Cleanup and optimization of Zicclsm. 2023-11-13 14:28:22 -06:00
Rose Thompson
cc7a0b211a Cleanup. 2023-11-13 12:35:11 -06:00
David Harris
121f685fa2 Removed assign statement inside always block 2023-11-13 07:23:15 -08:00
David Harris
c44ae93e22 DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst 2023-11-12 20:23:27 -08:00
David Harris
065f3f3f6d DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst 2023-11-12 20:23:14 -08:00
David Harris
571c7d3be4 Divider cleanup 2023-11-12 19:41:12 -08:00
David Harris
f437336540 Explained sqrt preshifting 2023-11-12 10:05:54 -08:00
David Harris
7c50b2c571 Renamed qsel to uslc and simplified radix2 uslc 2023-11-12 06:36:57 -08:00
David Harris
002034845a fdivsqrt comment improvements 2023-11-12 06:15:47 -08:00
David Harris
6ac83c776e Cleaned up number of bits in fdivsqrt 2023-11-11 15:50:06 -08:00
David Harris
2bf5143163 Bug fixes related to size of fpdivsqrt bit count and number of cycles 2023-11-11 05:58:53 -08:00
David Harris
d5ba8fc5e6 fdivsqrt parameter cleanup 2023-11-10 18:33:08 -08:00
David Harris
3cae2385ab Simplified out LOGRK parameter 2023-11-10 18:19:41 -08:00
David Harris
7d0d9dcebe divider cleanup 2023-11-10 18:01:13 -08:00
David Harris
03864642a7 fdivsqrt cleanup 2023-11-10 16:42:32 -08:00
David Harris
c5b12b7331 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-10 16:40:54 -08:00
Rose Thompson
c8cca8dfb8 Simplification. 2023-11-10 18:39:36 -06:00
Rose Thompson
c0e02ae190 Found another bug in the RTL's Zicclsm alignment. 2023-11-10 18:26:55 -06:00
Rose Thompson
02ab9fe99c Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues. 2023-11-10 17:58:42 -06:00
Rose Thompson
84d86b1994 Fixed spill bugs in the aligner. 2023-11-10 17:18:45 -06:00
David Harris
3108b58290 Simplified integer postnormalization shift 2023-11-10 14:55:36 -08:00
David Harris
b315ead575 Simplified IntDivNormShift 2023-11-10 14:28:57 -08:00
Rose Thompson
b74bfbeefd Merge branch 'main' into Zicclsm 2023-11-10 16:15:32 -06:00
Rose Thompson
9abd26aad9 Fixed bug which broke the non Zicclsm configs. 2023-11-10 16:08:04 -06:00
David Harris
2903791820 Simplified cycle count logic 2023-11-10 14:00:27 -08:00
David Harris
8f87860146 Reduced duplicated logic in fdivsqrtcycles 2023-11-10 11:25:54 -08:00
David Harris
255873a50c Divsqrt cleanup: change Q to U, commenting code 2023-11-10 11:21:02 -08:00
David Harris
953c53d065 fdivsqrt parameter cleanup 2023-11-10 09:11:15 -08:00
David Harris
4c106215f4 Started cleaning up shifting leading 1 in fdivsqrt 2023-11-10 08:46:55 -08:00
naichewa
5ce16dcb63 Cleanup 2023-11-09 16:52:55 -08:00
naichewa
3052a68d84 Remove old 2/4 bit logic, add comments, 
clean up unused signals
 2023-11-09 16:48:11 -08:00
naichewa
b13b8feee4 updated to-do comments 2023-11-08 15:28:51 -08:00
naichewa
d67badfc60 fix hardware interlock, hold mode deassert 2023-11-08 15:20:51 -08:00
Rose Thompson
44c60a3e76 Merge pull request #455 from davidharrishmc/dev 
Bit manipulation imperas config, fsqrt code changes to match chapter
 2023-11-08 08:27:15 -08:00
naichewa
a5837eb62c fifo fixes and edge case testing 2023-11-07 17:59:46 -08:00
David Harris
637cc3b78a Reparitioned sign logic in fdivsqrt to match paper 2023-11-06 14:11:42 -08:00
David Harris
4de21c206f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-03 16:04:10 -07:00
naichewa
6cdeb671bb Merge branch 'main' into spi 2023-11-03 13:15:15 -07:00
David Harris
7a56a66927 set default USE_SRAM=0 in memories; cleaned up synthesis script grep for cvw_t 2023-11-03 06:37:05 -07:00
David Harris
1f2899de14 Modified rams to take USE_SRAM rather than P to facilitate synthesis 2023-11-03 05:44:13 -07:00
David Harris
dd072c80f2 Updated testbenches to capture InstrM because it may be optimized out of IFU 2023-11-03 05:24:15 -07:00
David Harris
402538e13c Temporary fix of InstrM to prevent testbench hanging 2023-11-03 04:59:44 -07:00
David Harris
09aebbf252 Fixed regression error of watchdog timeout when PCM is optimized out of the IFU 2023-11-03 04:38:27 -07:00
naichewa
29e42b21df added test cases 2023-11-02 15:42:28 -07:00
Rose Thompson
0a4ed5515b Merge branch 'main' into Zicclsm 2023-11-02 12:55:51 -05:00
Rose Thompson
13333d3e82 Finally the d$ spill works. At least until the next bug. Definitely needs a lot of cleanup. 2023-11-01 14:25:18 -05:00
naichewa
a08356fdaa correct exclusion tags and reset testbench 2023-11-01 10:34:39 -07:00
naichewa
e3d8162279 harris code review 3 2023-11-01 10:14:15 -07:00
David Harris
31d9ec08cb Improved comments about memory read paths 2023-11-01 07:00:17 -07:00
naichewa
9aa8a7af3e comments, more test cases 2023-11-01 01:26:34 -07:00
Rose Thompson
5660eff57d Working through issues with the psill logic. 2023-10-31 18:50:13 -05:00
naichewa
fefb5adb8f code review harris 2023-10-31 12:27:41 -07:00
David Harris
680fb3f30b Conditionally instantiate hardware in ifu 2023-10-30 20:55:00 -07:00
David Harris
afabc52b61 Gated InstrOrigM and PCMReg when not needed 2023-10-30 20:05:37 -07:00
David Harris
2d17a991d8 rom1p1r code cleanup 2023-10-30 19:47:49 -07:00
David Harris
3f7c67882f rom1p1r code cleanup 2023-10-30 19:46:38 -07:00
David Harris
90a178e31e Made 2-bit AdrReg conditional on being needed 2023-10-30 19:13:43 -07:00
naichewa
7dd3f24d6c Merge branch 'main' into spi 2023-10-30 17:01:41 -07:00
naichewa
2330f4ee63 hardware interlock 2023-10-30 17:00:20 -07:00
Rose Thompson
2241976d29 Updated mmu to not generate trap on cacheable misaligned access when supported. 
Updated tests with David's help.
 2023-10-30 18:26:11 -05:00
Rose Thompson
f13b67b869 Preemptively fixed the bytemask bug before testing. 2023-10-30 15:47:46 -05:00
Rose Thompson
b5763e11e8 rv32gc now also works with the alignment module. Still not tested with misligned access. 2023-10-30 15:30:09 -05:00
Rose Thompson
9cd2e47783 Aligner is integrated and enabled in rv64gc and passes the regression test; however, there are no new tests. 2023-10-30 14:54:58 -05:00
Rose Thompson
569e3dc906 Finally lints cleanly. 2023-10-30 14:00:49 -05:00
David Harris
f6a7f707bd Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder. 2023-10-30 09:56:17 -07:00
David Harris
27b8ebb9bd Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported. 2023-10-30 07:06:34 -07:00
Rose Thompson
dce3c85105 Progress. 2023-10-27 16:31:22 -05:00
Rose Thompson
747f453bb5 Passes lint with some exceptions. Still need to add misaligned store support. 2023-10-27 14:41:42 -05:00
Rose Thompson
36ca64c567 At least have the aligner integrated, but not tested. 2023-10-27 13:55:16 -05:00
Rose Thompson
657409aec5 Addec ZICCLSM to config files and started on lsu instance. 2023-10-27 13:07:23 -05:00
Rose Thompson
6041bf20b3 The misaligned load alignment lints. 2023-10-27 11:41:49 -05:00
Rose Thompson
834c0df697 Added file. 2023-10-27 09:49:44 -05:00
Rose Thompson
449abef823 Progress on misaligned load/stores. 2023-10-27 09:35:44 -05:00
David Harris
734bf021d7 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-10-26 19:02:05 -07:00
Rose Thompson
06b5a92eff Updated comments about Interrupt and wfi. 2023-10-26 12:24:36 -05:00
Rose Thompson
4cd0584a11 Forgot to include this file in the last commit. 2023-10-26 12:20:42 -05:00
Rose Thompson
12763b7297 begin implemenation of Zicclsm. 2023-10-26 11:51:20 -05:00
Rose Thompson
3322ff915e Cleaned up the implementation changes for wfi. 2023-10-24 23:11:48 -05:00