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https://github.com/openhwgroup/cvw
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Better name for cache signals.
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parent
fd1c731ebb
commit
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10
src/cache/cache.sv
vendored
10
src/cache/cache.sv
vendored
@ -79,8 +79,8 @@ module cache import cvw::*; #(parameter cvw_t P,
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logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0];
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logic [NUMWAYS-1:0] HitWay, ValidWay;
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logic CacheHit;
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logic [NUMWAYS-1:0] VictimWay, DirtyWay, HitWayDirtyWay;
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logic LineDirty, HitWayLineDirty;
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logic [NUMWAYS-1:0] VictimWay, DirtyWay, HitDirtyWay;
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logic LineDirty, HitLineDirty;
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logic [TAGLEN-1:0] TagWay [NUMWAYS-1:0];
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logic [TAGLEN-1:0] Tag;
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logic [SETLEN-1:0] FlushAdr, NextFlushAdr, FlushAdrP1;
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@ -116,7 +116,7 @@ module cache import cvw::*; #(parameter cvw_t P,
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cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
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.clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, .SelWay,
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.SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay,
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.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitWayDirtyWay, .TagWay, .FlushStage, .InvalidateCache);
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.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitDirtyWay, .TagWay, .FlushStage, .InvalidateCache);
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// Select victim way for associative caches
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if(NUMWAYS > 1) begin:vict
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@ -128,7 +128,7 @@ module cache import cvw::*; #(parameter cvw_t P,
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assign CacheHit = |HitWay;
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assign LineDirty = |DirtyWay;
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assign HitWayLineDirty = |HitWayDirtyWay;
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assign HitLineDirty = |HitDirtyWay;
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// ReadDataLineWay is a 2d array of cache line len by number of ways.
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// Need to OR together each way in a bitwise manner.
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@ -219,7 +219,7 @@ module cache import cvw::*; #(parameter cvw_t P,
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cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
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.FlushStage, .CacheRW, .Stall,
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.CacheHit, .LineDirty, .HitWayLineDirty, .CacheStall, .CacheCommitted,
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.CacheHit, .LineDirty, .HitLineDirty, .CacheStall, .CacheCommitted,
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.CacheMiss, .CacheAccess, .SelAdr, .SelWay,
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.ClearDirty, .SetDirty, .SetValid, .ClearValid, .SelWriteback, .SelFlush,
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.FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
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4
src/cache/cachefsm.sv
vendored
4
src/cache/cachefsm.sv
vendored
@ -51,7 +51,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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// cache internals
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input logic CacheHit, // Exactly 1 way hits
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input logic LineDirty, // The selected line and way is dirty
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input logic HitWayLineDirty, // The cache hit way is dirty
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input logic HitLineDirty, // The cache hit way is dirty
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input logic FlushAdrFlag, // On last set of a cache flush
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input logic FlushWayFlag, // On the last way for any set of a cache flush
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output logic SelAdr, // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
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@ -95,7 +95,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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assign AnyMiss = (CacheRW[0] | CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
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assign AnyUpdateHit = (CacheRW[0]) & CacheHit; // exclusion-tag: icache storeAMO1
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assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit); // exclusion-tag: icache AnyUpdateHit
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assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit & HitWayLineDirty;
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assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit & HitLineDirty;
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assign CMOZeroNoEviction = CMOp[3] & ~LineDirty; // (hit or miss) with no writeback store zeros now
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assign CMOZeroEviction = CMOp[3] & LineDirty; // (hit or miss) with writeback dirty line
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assign CMOWriteback = CMOWritebackHit | CMOZeroEviction;
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6
src/cache/cacheway.sv
vendored
6
src/cache/cacheway.sv
vendored
@ -51,7 +51,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
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output logic [LINELEN-1:0] ReadDataLineWay,// This way's read data if valid
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output logic HitWay, // This way hits
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output logic ValidWay, // This way is valid
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output logic HitWayDirtyWay, // The hit way is dirty
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output logic HitDirtyWay, // The hit way is dirty
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output logic DirtyWay , // The selected way is dirty
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output logic [TAGLEN-1:0] TagWay); // This way's tag if valid
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@ -118,8 +118,8 @@ module cacheway import cvw::*; #(parameter cvw_t P,
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// AND portion of distributed tag multiplexer
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assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux
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assign HitWayDirtyWay = Dirty & ValidWay;
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assign DirtyWay = SelDirty & HitWayDirtyWay;
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assign HitDirtyWay = Dirty & ValidWay;
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assign DirtyWay = SelDirty & HitDirtyWay;
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assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]);
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/////////////////////////////////////////////////////////////////////////////////////////////
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