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https://github.com/openhwgroup/cvw
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divider cleanup
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03864642a7
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@ -30,12 +30,12 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
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input logic [P.FMTBITS-1:0] FmtE,
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input logic SqrtE,
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input logic IntDivE,
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input logic [P.DIVBLEN:0] IntResultBits,
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input logic [P.DIVBLEN:0] IntResultBitsE,
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output logic [P.DURLEN-1:0] CyclesE
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);
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logic [P.DURLEN+1:0] Nf, FPResultBits; // number of fractional bits
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logic [P.DIVBLEN:0] ResultBits; // number of result bits;
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logic [P.DURLEN+1:0] Nf, FPResultBitsE; // number of fractional bits
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logic [P.DIVBLEN:0] ResultBitsE; // number of result bits;
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// DIVN = P.NF+3
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// NS = NF + 1
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@ -72,16 +72,16 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
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// Integer division needs p fractional + r integer result bits
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// FP Division needs at least Nf fractional bits + 2 guard/round bits and one integer digit (LOG R integer bits) = Nf + 2 + r bits
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// FP Sqrt needs at least Nf fractional bits, 2 guard/round bits, and *** shift bits
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// The datapath produces rk bits per cycle, so Cycles = ceil (ResultBits / rk)
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// The datapath produces rk bits per cycle, so Cycles = ceil (ResultBitsE / rk)
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always_comb begin
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if (SqrtE) FPResultBits = Nf + 2 + 1; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 *** unclear why it works with just +1 rather than +2; is it related to DIVCOPIES logic below?
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else FPResultBits = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
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if (SqrtE) FPResultBitsE = Nf + 2 + 0; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 *** unclear why it works with just +1 and +0 rather than +2; is it related to DIVCOPIES logic below?
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else FPResultBitsE = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
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if (P.IDIV_ON_FPU) ResultBits = IntDivE ? IntResultBits : FPResultBits;
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else ResultBits = FPResultBits;
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if (P.IDIV_ON_FPU) ResultBitsE = IntDivE ? IntResultBitsE : FPResultBitsE;
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else ResultBitsE = FPResultBitsE;
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assign CyclesE = (ResultBits-1)/(P.RK) + 1; // ceil (ResultBits/rk)
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assign CyclesE = (ResultBitsE-1)/(P.RK) + 1; // ceil (ResultBitsE/rk)
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end
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/* verilator lint_on WIDTH */
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@ -54,7 +54,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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logic [P.NE+1:0] UeE; // Result Exponent (FP only)
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logic [P.DIVb:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input
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logic [P.DIVBLEN:0] mE, ell; // Leading zeros of inputs
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logic [P.DIVBLEN:0] IntResultBits; // bits in integer result
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logic [P.DIVBLEN:0] IntResultBitsE; // bits in integer result
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logic NumerZeroE; // Numerator is zero (X or A)
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logic AZeroE, BZeroE; // A or B is Zero for integer division
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logic SignedDivE; // signed division
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@ -126,7 +126,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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mux2 #(P.DIVBLEN+1) pmux(ZeroDiff, '0, ALTBE, p);
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/* verilator lint_off WIDTH */
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assign IntResultBits = P.LOGR + p; // Total number of result bits (r integer bits plus p fractional bits)
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assign IntResultBitsE = P.LOGR + p; // Total number of result bits (r integer bits plus p fractional bits)
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/* verilator lint_on WIDTH */
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// Integer special cases (terminate immediately)
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@ -137,7 +137,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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logic [P.LOGRK-1:0] IntTrunc, RightShiftX;
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logic [P.DIVBLEN:0] IntSteps;
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/* verilator lint_offf WIDTH */
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assign RightShiftX = P.RK - 1 - ((IntResultBits - 1) % P.RK); // Right shift amount
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assign RightShiftX = P.RK - 1 - ((IntResultBitsE - 1) % P.RK); // Right shift amount
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assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in n steps
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/* verilator lint_on WIDTH */
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end else begin // radix 2 1 copy doesn't require shifting
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@ -190,7 +190,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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flopen #(P.NE+2) expreg(clk, IFDivStartE, UeE, UeM);
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// Number of FSM cycles (to FSM)
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fdivsqrtcycles #(P) cyclecalc(.FmtE, .SqrtE, .IntDivE, .IntResultBits, .CyclesE);
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fdivsqrtcycles #(P) cyclecalc(.FmtE, .SqrtE, .IntDivE, .IntResultBitsE, .CyclesE);
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if (P.IDIV_ON_FPU) begin:intpipelineregs
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logic [P.DIVBLEN:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE;
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@ -83,7 +83,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
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assign BadNaNBox = ~(Fmt|(&In[P.FLEN-1:P.LEN1])); // Check NaN boxing
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always_comb
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if (BadNaNBox) begin
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// PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, In[P.LEN1-P.NE1-3:0]};
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PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}};
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end else
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PostBox = In;
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@ -143,8 +142,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
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if (BadNaNBox) begin
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case (Fmt)
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P.FMT: PostBox = In;
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// P.FMT1: PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, In[P.LEN1-P.NE1-3:0]};
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// P.FMT2: PostBox = {{(P.FLEN-P.LEN2){1'b1}}, 1'b1, {(P.NE2+1){1'b1}}, In[P.LEN2-P.NE2-3:0]};
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P.FMT1: PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}};
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P.FMT2: PostBox = {{(P.FLEN-P.LEN2){1'b1}}, 1'b1, {(P.NE2+1){1'b1}}, {(P.LEN2-P.NE2-2){1'b0}}};
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default: PostBox = 'x;
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@ -230,9 +227,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
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if (BadNaNBox) begin
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case (Fmt)
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2'b11: PostBox = In;
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// 2'b01: PostBox = {{(P.Q_LEN-P.D_LEN){1'b1}}, 1'b1, {(P.D_NE+1){1'b1}}, In[P.D_LEN-P.D_NE-3:0]};
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// 2'b00: PostBox = {{(P.Q_LEN-P.S_LEN){1'b1}}, 1'b1, {(P.S_NE+1){1'b1}}, In[P.S_LEN-P.S_NE-3:0]};
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// 2'b10: PostBox = {{(P.Q_LEN-P.H_LEN){1'b1}}, 1'b1, {(P.H_NE+1){1'b1}}, In[P.H_LEN-P.H_NE-3:0]};
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2'b01: PostBox = {{(P.Q_LEN-P.D_LEN){1'b1}}, 1'b1, {(P.D_NE+1){1'b1}}, {(P.D_LEN-P.D_NE-2){1'b0}}};
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2'b00: PostBox = {{(P.Q_LEN-P.S_LEN){1'b1}}, 1'b1, {(P.S_NE+1){1'b1}}, {(P.S_LEN-P.S_NE-2){1'b0}}};
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2'b10: PostBox = {{(P.Q_LEN-P.H_LEN){1'b1}}, 1'b1, {(P.H_NE+1){1'b1}}, {(P.H_LEN-P.H_NE-2){1'b0}}};
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