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divider cleanup

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This commit is contained in:
David Harris 2023-11-10 18:01:13 -08:00
parent 03864642a7
commit 7d0d9dcebe
3 changed files with 13 additions and 19 deletions
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18
src/fpu/fdivsqrt/fdivsqrtcycles.sv
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@ -30,12 +30,12 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
input logic [P.FMTBITS-1:0] FmtE,
input logic SqrtE,
input logic IntDivE,
input logic [P.DIVBLEN:0] IntResultBits,
input logic [P.DIVBLEN:0] IntResultBitsE,
output logic [P.DURLEN-1:0] CyclesE
);
logic [P.DURLEN+1:0] Nf, FPResultBits; // number of fractional bits
logic [P.DIVBLEN:0] ResultBits; // number of result bits;
logic [P.DURLEN+1:0] Nf, FPResultBitsE; // number of fractional bits
logic [P.DIVBLEN:0] ResultBitsE; // number of result bits;
// DIVN = P.NF+3
// NS = NF + 1
@ -72,16 +72,16 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
// Integer division needs p fractional + r integer result bits
// FP Division needs at least Nf fractional bits + 2 guard/round bits and one integer digit (LOG R integer bits) = Nf + 2 + r bits
// FP Sqrt needs at least Nf fractional bits, 2 guard/round bits, and *** shift bits
// The datapath produces rk bits per cycle, so Cycles = ceil (ResultBits / rk)
// The datapath produces rk bits per cycle, so Cycles = ceil (ResultBitsE / rk)
always_comb begin
if (SqrtE) FPResultBits = Nf + 2 + 1; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 *** unclear why it works with just +1 rather than +2; is it related to DIVCOPIES logic below?
else FPResultBits = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
if (SqrtE) FPResultBitsE = Nf + 2 + 0; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 *** unclear why it works with just +1 and +0 rather than +2; is it related to DIVCOPIES logic below?
else FPResultBitsE = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
if (P.IDIV_ON_FPU) ResultBits = IntDivE ? IntResultBits : FPResultBits;
else ResultBits = FPResultBits;
if (P.IDIV_ON_FPU) ResultBitsE = IntDivE ? IntResultBitsE : FPResultBitsE;
else ResultBitsE = FPResultBitsE;
assign CyclesE = (ResultBits-1)/(P.RK) + 1; // ceil (ResultBits/rk)
assign CyclesE = (ResultBitsE-1)/(P.RK) + 1; // ceil (ResultBitsE/rk)
end
/* verilator lint_on WIDTH */

8
src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -54,7 +54,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
logic [P.NE+1:0] UeE; // Result Exponent (FP only)
logic [P.DIVb:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input
logic [P.DIVBLEN:0] mE, ell; // Leading zeros of inputs
logic [P.DIVBLEN:0] IntResultBits; // bits in integer result
logic [P.DIVBLEN:0] IntResultBitsE; // bits in integer result
logic NumerZeroE; // Numerator is zero (X or A)
logic AZeroE, BZeroE; // A or B is Zero for integer division
logic SignedDivE; // signed division
@ -126,7 +126,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
mux2 #(P.DIVBLEN+1) pmux(ZeroDiff, '0, ALTBE, p);
/* verilator lint_off WIDTH */
assign IntResultBits = P.LOGR + p; // Total number of result bits (r integer bits plus p fractional bits)
assign IntResultBitsE = P.LOGR + p; // Total number of result bits (r integer bits plus p fractional bits)
/* verilator lint_on WIDTH */
// Integer special cases (terminate immediately)
@ -137,7 +137,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
logic [P.LOGRK-1:0] IntTrunc, RightShiftX;
logic [P.DIVBLEN:0] IntSteps;
/* verilator lint_offf WIDTH */
assign RightShiftX = P.RK - 1 - ((IntResultBits - 1) % P.RK); // Right shift amount
assign RightShiftX = P.RK - 1 - ((IntResultBitsE - 1) % P.RK); // Right shift amount
assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in n steps
/* verilator lint_on WIDTH */
end else begin // radix 2 1 copy doesn't require shifting
@ -190,7 +190,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
flopen #(P.NE+2) expreg(clk, IFDivStartE, UeE, UeM);
// Number of FSM cycles (to FSM)
fdivsqrtcycles #(P) cyclecalc(.FmtE, .SqrtE, .IntDivE, .IntResultBits, .CyclesE);
fdivsqrtcycles #(P) cyclecalc(.FmtE, .SqrtE, .IntDivE, .IntResultBitsE, .CyclesE);
if (P.IDIV_ON_FPU) begin:intpipelineregs
logic [P.DIVBLEN:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE;

6
src/fpu/unpackinput.sv
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@ -83,7 +83,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
assign BadNaNBox = ~(Fmt|(&In[P.FLEN-1:P.LEN1])); // Check NaN boxing
always_comb
if (BadNaNBox) begin
// PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, In[P.LEN1-P.NE1-3:0]};
PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}};
end else
PostBox = In;
@ -143,8 +142,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
if (BadNaNBox) begin
case (Fmt)
P.FMT: PostBox = In;
// P.FMT1: PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, In[P.LEN1-P.NE1-3:0]};
// P.FMT2: PostBox = {{(P.FLEN-P.LEN2){1'b1}}, 1'b1, {(P.NE2+1){1'b1}}, In[P.LEN2-P.NE2-3:0]};
P.FMT1: PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}};
P.FMT2: PostBox = {{(P.FLEN-P.LEN2){1'b1}}, 1'b1, {(P.NE2+1){1'b1}}, {(P.LEN2-P.NE2-2){1'b0}}};
default: PostBox = 'x;
@ -230,9 +227,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
if (BadNaNBox) begin
case (Fmt)
2'b11: PostBox = In;
// 2'b01: PostBox = {{(P.Q_LEN-P.D_LEN){1'b1}}, 1'b1, {(P.D_NE+1){1'b1}}, In[P.D_LEN-P.D_NE-3:0]};
// 2'b00: PostBox = {{(P.Q_LEN-P.S_LEN){1'b1}}, 1'b1, {(P.S_NE+1){1'b1}}, In[P.S_LEN-P.S_NE-3:0]};
// 2'b10: PostBox = {{(P.Q_LEN-P.H_LEN){1'b1}}, 1'b1, {(P.H_NE+1){1'b1}}, In[P.H_LEN-P.H_NE-3:0]};
2'b01: PostBox = {{(P.Q_LEN-P.D_LEN){1'b1}}, 1'b1, {(P.D_NE+1){1'b1}}, {(P.D_LEN-P.D_NE-2){1'b0}}};
2'b00: PostBox = {{(P.Q_LEN-P.S_LEN){1'b1}}, 1'b1, {(P.S_NE+1){1'b1}}, {(P.S_LEN-P.S_NE-2){1'b0}}};
2'b10: PostBox = {{(P.Q_LEN-P.H_LEN){1'b1}}, 1'b1, {(P.H_NE+1){1'b1}}, {(P.H_LEN-P.H_NE-2){1'b0}}};