Fixed part of issue #405.

The non-cache version of the bus controller did not have the correct supression of BusCommitted for a read only controller.
This commit is contained in:
Rose Thompson 2024-01-15 17:29:00 -06:00
parent 83df3dfe83
commit 614a83331f
2 changed files with 5 additions and 3 deletions

View File

@ -64,7 +64,7 @@ module ahbinterface #(
assign HWSTRB = '0;
end
busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW,
busfsm #(~LSU) busfsm(.HCLK, .HRESETn, .Flush, .BusRW,
.BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY,
.HTRANS, .HWRITE);

View File

@ -28,7 +28,9 @@
////////////////////////////////////////////////////////////////////////////////////////////////
// HCLK and clk must be the same clock!
module busfsm (
module busfsm #(
parameter READ_ONLY
)(
input logic HCLK,
input logic HRESETn,
@ -70,7 +72,7 @@ module busfsm (
// (CurrState == DATA_PHASE & ~BusRW[0]); // possible optimization here. fails uart test, but i'm not sure the failure is valid.
(CurrState == DATA_PHASE);
assign BusCommitted = CurrState != ADR_PHASE;
assign BusCommitted = CurrState != ADR_PHASE & ~(READ_ONLY & CurrState == MEM3);
assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) ? AHB_NONSEQ : AHB_IDLE;
assign HWRITE = BusRW[0];