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https://github.com/openhwgroup/cvw
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Fixed part of issue #405.
The non-cache version of the bus controller did not have the correct supression of BusCommitted for a read only controller.
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@ -64,7 +64,7 @@ module ahbinterface #(
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assign HWSTRB = '0;
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end
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busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW,
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busfsm #(~LSU) busfsm(.HCLK, .HRESETn, .Flush, .BusRW,
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.BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY,
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.HTRANS, .HWRITE);
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@ -28,7 +28,9 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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// HCLK and clk must be the same clock!
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module busfsm (
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module busfsm #(
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parameter READ_ONLY
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)(
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input logic HCLK,
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input logic HRESETn,
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@ -70,7 +72,7 @@ module busfsm (
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// (CurrState == DATA_PHASE & ~BusRW[0]); // possible optimization here. fails uart test, but i'm not sure the failure is valid.
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(CurrState == DATA_PHASE);
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assign BusCommitted = CurrState != ADR_PHASE;
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assign BusCommitted = CurrState != ADR_PHASE & ~(READ_ONLY & CurrState == MEM3);
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) ? AHB_NONSEQ : AHB_IDLE;
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assign HWRITE = BusRW[0];
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