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"Resolved" ram preload issues by replacing the RAM's types with bit from logic. Tested fpga synthesis.

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This commit is contained in:
Rose Thompson 2023-12-20 12:05:25 -06:00
parent 9ee1ffe8fe
commit 9de434a61b
2 changed files with 2 additions and 9 deletions
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2
src/generic/mem/ram1p1rwbe.sv
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@ -42,7 +42,7 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:0] RAM[DEPTH-1:0];
bit [WIDTH-1:0] RAM[DEPTH-1:0];
// ***************************************************************************
// TRUE SRAM macro

9
src/uncore/ram_ahb.sv
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@ -51,7 +51,6 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
logic memwrite, memwriteD, memread;
logic nextHREADYRam;
logic DelayReady;
logic [P.XLEN-1:0] HRDATA2;
// a new AHB transactions starts when HTRANS requests a transaction,
// the peripheral is selected, and the previous transaction is completing
@ -73,13 +72,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
// single-ported RAM
ram1p1rwbe #(P.USE_SRAM, RANGE/8, P.XLEN, PRELOAD) memory(.clk(HCLK), .ce(1'b1),
.addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HRDATA2));
//assign HREADRam = HRDATA2 === 'bx ? 64'hdeadbeefdeadbeef : HRDATA2;
// **** RT: MAJOR BUG can't leave in for anything. Will cause synthesis issues.
// PRIV sv48-svadu test not working without it.
//assign HREADRam = HRDATA2 === 'bx ? 64'h0 : HRDATA2;
assign HREADRam = HRDATA2;
.addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam));
// use this to add arbitrary latency to ram. Helps test AHB controller correctness
if(`RAM_LATENCY > 0) begin