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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Removed other unused signals from Verilog
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f89fd8a7fe
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d3ce683e06
@ -52,7 +52,7 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)(
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// AHB-Lite external signals
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output logic HCLK, HRESETn,
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input logic HREADY, // AHB peripheral ready
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input logic HRESP, // AHB peripheral response. 0: OK 1: Error
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input logic HRESP, // AHB peripheral response. 0: OK 1: Error. Presently ignored.
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output logic [PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration
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output logic [AHBW-1:0] HWDATA, // AHB Write data after arbitration
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output logic [XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration
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@ -41,7 +41,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
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input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision
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input logic [6:0] OpD, // bits 6:0 of instruction
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input logic [4:0] Rs2D, // bits 24:20 of instruction
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input logic [2:0] Funct3D, Funct3E, // bits 14:12 of instruction - may contain rounding mode
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input logic [2:0] Funct3D, // bits 14:12 of instruction - may contain rounding mode
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// input mux selections
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output logic XEnD, YEnD, ZEnD, // enable inputs
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output logic XEnE, YEnE, ZEnE, // enable inputs
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@ -30,8 +30,7 @@ module fdivsqrtexpcalc import cvw::*; #(parameter cvw_t P) (
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input logic [P.FMTBITS-1:0] Fmt,
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input logic [P.NE-1:0] Xe, Ye, // input exponents
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input logic Sqrt,
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input logic XZero,
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input logic [P.DIVBLEN-1:0] ell, m, // number of leading 0s in Xe and Ye
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input logic [P.DIVBLEN-1:0] ell, m, // number of leading 0s in Xe and Ye
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output logic [P.NE+1:0] Ue // result exponent
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);
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@ -210,7 +210,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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flopen #(P.DIVb+4) dreg(clk, IFDivStartE, {3'b000, Dnorm}, D);
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// Floating-point exponent
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fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Ue(UeE));
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fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .ell, .m(mE), .Ue(UeE));
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flopen #(P.NE+2) expreg(clk, IFDivStartE, UeE, UeM);
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// Number of FSM cycles (to FSM)
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@ -167,7 +167,7 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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// calculate FP control signals
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fctrl #(P) fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]),
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.Funct3E, .IntDivE, .InstrD,
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.IntDivE, .InstrD,
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.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
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.reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM,
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.FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .FpLoadStoreM,
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@ -32,7 +32,6 @@ module hazard import cvw::*; #(parameter cvw_t P) (
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input logic LSUStallM, IFUStallF,
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input logic FCvtIntStallD, FPUStallD,
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input logic DivBusyE, FDivBusyE,
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input logic EcallFaultM, BreakpointFaultM,
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input logic wfiM, IntPendingM,
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// Stall & flush outputs
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output logic StallF, StallD, StallE, StallM, StallW,
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@ -45,7 +45,6 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
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logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult, PreALUResult; // Intermediate Signals
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logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux
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logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux
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logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux
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logic Carry, Neg; // Flags: carry out, negative
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logic LT, LTU; // Less than, Less than unsigned
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logic Asign, Bsign; // Sign bits of A, B
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@ -103,7 +103,6 @@ module controller import cvw::*; #(parameter cvw_t P) (
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logic BaseRegWriteD; // Indicates if Base instruction register write instruction
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logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu
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logic BaseALUSrcBD; // Base instruction ALU B source select signal
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logic [2:0] ALUControlD; // Determines ALU operation
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logic ALUSrcAD, ALUSrcBD; // ALU inputs
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logic ALUResultSrcD, W64D, MDUD; // ALU result, is RV64 W-type, is multiply/divide instruction
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logic CSRZeroSrcD; // Ignore setting and clearing zeros to CSR
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@ -118,7 +117,6 @@ module controller import cvw::*; #(parameter cvw_t P) (
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logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals
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logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor
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logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions
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logic ALUOpE; // 0 for address generationm 1 for ALU operations
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logic BranchTakenE; // Branch is taken
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logic eqE, ltE; // Comparator outputs
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logic unused;
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@ -33,7 +33,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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// Command from CPU
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input logic InvalidateICacheM, // Clears all instruction cache valid bits
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input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
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input logic InstrValidD, InstrValidE, InstrValidM,
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input logic InstrValidD, InstrValidE,
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input logic BranchD, BranchE,
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input logic JumpD, JumpE,
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// Bus interface
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@ -103,7 +103,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
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logic [P.XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
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logic [P.XLEN-1:0] PCSpillNextF; // Next PCF after possible + 2 to handle spill
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logic [P.XLEN-1:0] PCLinkD; // PCF2or4F delayed 1 cycle. This is next PC after a control flow instruction (br or j)
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logic [P.XLEN-1:2] PCPlus4F; // PCPlus4F is always PCF + 4. Fancy way to compute PCPlus2or4F
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logic [P.XLEN-1:0] PCD; // Decode stage instruction address
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logic [P.XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence
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@ -228,7 +227,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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logic [P.PA_BITS-1:0] ICacheBusAdr;
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logic ICacheBusAck;
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logic [1:0] CacheBusRW, BusRW, CacheRWF;
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logic [1:0] CacheBusRWTemp;
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assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
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assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
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@ -40,7 +40,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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input logic [1:0] AtomicM, // Atomic memory operation
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input logic FlushDCacheM, // Flush D cache to next level of memory
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input logic [3:0] CMOpM, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
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input logic LSUPrefetchM, // Prefetch
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input logic LSUPrefetchM, // Prefetch; presently unused
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output logic CommittedM, // Delay interrupts while memory operation in flight
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output logic SquashSCW, // Store conditional failed disable write to GPR
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output logic DCacheMiss, // D cache miss for performance counters
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@ -38,8 +38,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
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input logic [P.XLEN-1:0] SrcAM, IEUAdrM, // SrcA and memory address from IEU
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input logic CSRReadM, CSRWriteM, // read or write CSR
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input logic TrapM, // trap is occurring
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input logic mretM, sretM, wfiM, // return or WFI instruction
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input logic IntPendingM, // at least one interrupt is pending and could occur if enabled
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input logic mretM, sretM, // return instruction
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input logic InterruptM, // interrupt is occurring
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input logic ExceptionM, // interrupt is occurring
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input logic MTimerInt, // timer interrupt
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@ -248,7 +247,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
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csrs #(P) csrs(.clk, .reset,
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.CSRSWriteM, .STrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
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.STATUS_TVM, .MCOUNTEREN_TM(MCOUNTEREN_REGW[1]),
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.STATUS_TVM,
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.CSRWriteValM, .PrivilegeModeW,
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.CSRSReadValM, .STVEC_REGW, .SEPC_REGW,
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.SCOUNTEREN_REGW,
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@ -35,7 +35,6 @@ module csrs import cvw::*; #(parameter cvw_t P) (
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input logic [P.XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW,
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input logic [4:0] NextCauseM,
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input logic STATUS_TVM,
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input logic MCOUNTEREN_TM, // TM bit (1) of MCOUNTEREN; cause illegal instruction when trying to access STIMECMP if clear
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input logic [P.XLEN-1:0] CSRWriteValM,
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input logic [1:0] PrivilegeModeW,
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output logic [P.XLEN-1:0] CSRSReadValM, STVEC_REGW,
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@ -29,7 +29,7 @@
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module privdec import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic StallM, StallW, FlushW,
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input logic StallW, FlushW,
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input logic [31:15] InstrM, // privileged instruction function field
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input logic PrivilegedM, // is this a privileged instruction (from IEU controller)
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input logic IllegalIEUFPUInstrM, // Not a legal IEU instruction
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@ -93,7 +93,6 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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input logic InvalidateICacheM, // fence instruction
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output logic BigEndianM, // Use big endian in current privilege mode
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// Fault outputs
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output logic BreakpointFaultM, EcallFaultM, // breakpoint and Ecall traps should retire
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output logic wfiM, IntPendingM // Stall in Memory stage for WFI until interrupt pending or timeout
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);
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@ -114,6 +113,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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logic InterruptM; // interrupt occuring
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logic ExceptionM; // Memory stage instruction caused a fault
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logic HPTWInstrAccessFaultM; // Hardware page table access fault while fetching instruction PTE
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logic BreakpointFaultM, EcallFaultM; // breakpoint and Ecall traps should retire
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logic wfiW;
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@ -122,7 +122,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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.STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
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// decode privileged instructions
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privdec #(P) pmd(.clk, .reset, .StallM, .StallW, .FlushW, .InstrM(InstrM[31:15]),
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privdec #(P) pmd(.clk, .reset, .StallW, .FlushW, .InstrM(InstrM[31:15]),
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.PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM,
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.PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM,
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.EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .wfiW, .sfencevmaM);
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@ -130,7 +130,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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// Control and Status Registers
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csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
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.InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, .PC2NextF,
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.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
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.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM,
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.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
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.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
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.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,
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@ -68,11 +68,10 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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// Watermark signals - TransmitReadMark = ip[0], ReceiveWriteMark = ip[1]
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logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark;
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logic TransmitFIFOWriteFull, TransmitFIFOReadEmpty;
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logic TransmitFIFOReadIncrement;
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logic TransmitFIFOWriteIncrement;
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logic ReceiveFIFOReadIncrement;
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logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty;
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logic [7:0] TransmitFIFOReadData, ReceiveFIFOWriteData;
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logic [7:0] TransmitFIFOReadData;
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logic [2:0] TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel;
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logic [7:0] ReceiveShiftRegEndian; // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
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@ -92,7 +91,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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// Frame counting signals
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logic [3:0] FrameCount; // Counter for number of frames in transmission
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logic [3:0] ReceivePenultimateFrameCount; // Counter
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logic ReceivePenultimateFrame; // High when penultimate frame in transmission has been reached
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// State fsm signals
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@ -158,7 +158,6 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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logic DCacheAccess;
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logic ICacheMiss;
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logic ICacheAccess;
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logic BreakpointFaultM, EcallFaultM;
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logic InstrUpdateDAF;
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logic BigEndianM;
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logic FCvtIntE;
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@ -170,7 +169,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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// instruction fetch unit: PC, branch prediction, instruction cache
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ifu #(P) ifu(.clk, .reset,
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.StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.InstrValidM, .InstrValidE, .InstrValidD,
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.InstrValidE, .InstrValidD,
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.BranchD, .BranchE, .JumpD, .JumpE, .ICacheStallF,
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// Fetch
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.HRDATA, .PCSpillF, .IFUHADDR, .PC2NextF,
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@ -270,7 +269,6 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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.LSUStallM, .IFUStallF,
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.FCvtIntStallD, .FPUStallD,
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.DivBusyE, .FDivBusyE,
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.EcallFaultM, .BreakpointFaultM,
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.wfiM, .IntPendingM,
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// Stall & flush outputs
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.StallF, .StallD, .StallE, .StallM, .StallW,
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@ -298,7 +296,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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.PrivilegeModeW, .SATP_REGW,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE, .BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM);
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.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE, .wfiM, .IntPendingM, .BigEndianM);
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end else begin
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assign CSRReadValW = 0;
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assign UnalignedPCNextF = PC2NextF;
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