Removed other unused signals from Verilog

This commit is contained in:
David Harris 2023-11-20 23:37:56 -08:00
parent f89fd8a7fe
commit d3ce683e06
16 changed files with 16 additions and 29 deletions

View File

@ -52,7 +52,7 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)(
// AHB-Lite external signals
output logic HCLK, HRESETn,
input logic HREADY, // AHB peripheral ready
input logic HRESP, // AHB peripheral response. 0: OK 1: Error
input logic HRESP, // AHB peripheral response. 0: OK 1: Error. Presently ignored.
output logic [PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration
output logic [AHBW-1:0] HWDATA, // AHB Write data after arbitration
output logic [XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration

View File

@ -41,7 +41,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision
input logic [6:0] OpD, // bits 6:0 of instruction
input logic [4:0] Rs2D, // bits 24:20 of instruction
input logic [2:0] Funct3D, Funct3E, // bits 14:12 of instruction - may contain rounding mode
input logic [2:0] Funct3D, // bits 14:12 of instruction - may contain rounding mode
// input mux selections
output logic XEnD, YEnD, ZEnD, // enable inputs
output logic XEnE, YEnE, ZEnE, // enable inputs

View File

@ -30,8 +30,7 @@ module fdivsqrtexpcalc import cvw::*; #(parameter cvw_t P) (
input logic [P.FMTBITS-1:0] Fmt,
input logic [P.NE-1:0] Xe, Ye, // input exponents
input logic Sqrt,
input logic XZero,
input logic [P.DIVBLEN-1:0] ell, m, // number of leading 0s in Xe and Ye
input logic [P.DIVBLEN-1:0] ell, m, // number of leading 0s in Xe and Ye
output logic [P.NE+1:0] Ue // result exponent
);

View File

@ -210,7 +210,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
flopen #(P.DIVb+4) dreg(clk, IFDivStartE, {3'b000, Dnorm}, D);
// Floating-point exponent
fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Ue(UeE));
fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .ell, .m(mE), .Ue(UeE));
flopen #(P.NE+2) expreg(clk, IFDivStartE, UeE, UeM);
// Number of FSM cycles (to FSM)

View File

@ -167,7 +167,7 @@ module fpu import cvw::*; #(parameter cvw_t P) (
// calculate FP control signals
fctrl #(P) fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]),
.Funct3E, .IntDivE, .InstrD,
.IntDivE, .InstrD,
.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
.reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM,
.FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .FpLoadStoreM,

View File

@ -32,7 +32,6 @@ module hazard import cvw::*; #(parameter cvw_t P) (
input logic LSUStallM, IFUStallF,
input logic FCvtIntStallD, FPUStallD,
input logic DivBusyE, FDivBusyE,
input logic EcallFaultM, BreakpointFaultM,
input logic wfiM, IntPendingM,
// Stall & flush outputs
output logic StallF, StallD, StallE, StallM, StallW,

View File

@ -45,7 +45,6 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult, PreALUResult; // Intermediate Signals
logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux
logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux
logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux
logic Carry, Neg; // Flags: carry out, negative
logic LT, LTU; // Less than, Less than unsigned
logic Asign, Bsign; // Sign bits of A, B

View File

@ -103,7 +103,6 @@ module controller import cvw::*; #(parameter cvw_t P) (
logic BaseRegWriteD; // Indicates if Base instruction register write instruction
logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu
logic BaseALUSrcBD; // Base instruction ALU B source select signal
logic [2:0] ALUControlD; // Determines ALU operation
logic ALUSrcAD, ALUSrcBD; // ALU inputs
logic ALUResultSrcD, W64D, MDUD; // ALU result, is RV64 W-type, is multiply/divide instruction
logic CSRZeroSrcD; // Ignore setting and clearing zeros to CSR
@ -118,7 +117,6 @@ module controller import cvw::*; #(parameter cvw_t P) (
logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals
logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor
logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions
logic ALUOpE; // 0 for address generationm 1 for ALU operations
logic BranchTakenE; // Branch is taken
logic eqE, ltE; // Comparator outputs
logic unused;

View File

@ -33,7 +33,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
// Command from CPU
input logic InvalidateICacheM, // Clears all instruction cache valid bits
input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
input logic InstrValidD, InstrValidE, InstrValidM,
input logic InstrValidD, InstrValidE,
input logic BranchD, BranchE,
input logic JumpD, JumpE,
// Bus interface
@ -103,7 +103,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
logic [P.XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
logic [P.XLEN-1:0] PCSpillNextF; // Next PCF after possible + 2 to handle spill
logic [P.XLEN-1:0] PCLinkD; // PCF2or4F delayed 1 cycle. This is next PC after a control flow instruction (br or j)
logic [P.XLEN-1:2] PCPlus4F; // PCPlus4F is always PCF + 4. Fancy way to compute PCPlus2or4F
logic [P.XLEN-1:0] PCD; // Decode stage instruction address
logic [P.XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence
@ -228,7 +227,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
logic [P.PA_BITS-1:0] ICacheBusAdr;
logic ICacheBusAck;
logic [1:0] CacheBusRW, BusRW, CacheRWF;
logic [1:0] CacheBusRWTemp;
assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;

View File

@ -40,7 +40,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
input logic [1:0] AtomicM, // Atomic memory operation
input logic FlushDCacheM, // Flush D cache to next level of memory
input logic [3:0] CMOpM, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
input logic LSUPrefetchM, // Prefetch
input logic LSUPrefetchM, // Prefetch; presently unused
output logic CommittedM, // Delay interrupts while memory operation in flight
output logic SquashSCW, // Store conditional failed disable write to GPR
output logic DCacheMiss, // D cache miss for performance counters

View File

@ -38,8 +38,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
input logic [P.XLEN-1:0] SrcAM, IEUAdrM, // SrcA and memory address from IEU
input logic CSRReadM, CSRWriteM, // read or write CSR
input logic TrapM, // trap is occurring
input logic mretM, sretM, wfiM, // return or WFI instruction
input logic IntPendingM, // at least one interrupt is pending and could occur if enabled
input logic mretM, sretM, // return instruction
input logic InterruptM, // interrupt is occurring
input logic ExceptionM, // interrupt is occurring
input logic MTimerInt, // timer interrupt
@ -248,7 +247,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
csrs #(P) csrs(.clk, .reset,
.CSRSWriteM, .STrapM, .CSRAdrM,
.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
.STATUS_TVM, .MCOUNTEREN_TM(MCOUNTEREN_REGW[1]),
.STATUS_TVM,
.CSRWriteValM, .PrivilegeModeW,
.CSRSReadValM, .STVEC_REGW, .SEPC_REGW,
.SCOUNTEREN_REGW,

View File

@ -35,7 +35,6 @@ module csrs import cvw::*; #(parameter cvw_t P) (
input logic [P.XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW,
input logic [4:0] NextCauseM,
input logic STATUS_TVM,
input logic MCOUNTEREN_TM, // TM bit (1) of MCOUNTEREN; cause illegal instruction when trying to access STIMECMP if clear
input logic [P.XLEN-1:0] CSRWriteValM,
input logic [1:0] PrivilegeModeW,
output logic [P.XLEN-1:0] CSRSReadValM, STVEC_REGW,

View File

@ -29,7 +29,7 @@
module privdec import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
input logic StallM, StallW, FlushW,
input logic StallW, FlushW,
input logic [31:15] InstrM, // privileged instruction function field
input logic PrivilegedM, // is this a privileged instruction (from IEU controller)
input logic IllegalIEUFPUInstrM, // Not a legal IEU instruction

View File

@ -93,7 +93,6 @@ module privileged import cvw::*; #(parameter cvw_t P) (
input logic InvalidateICacheM, // fence instruction
output logic BigEndianM, // Use big endian in current privilege mode
// Fault outputs
output logic BreakpointFaultM, EcallFaultM, // breakpoint and Ecall traps should retire
output logic wfiM, IntPendingM // Stall in Memory stage for WFI until interrupt pending or timeout
);
@ -114,6 +113,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
logic InterruptM; // interrupt occuring
logic ExceptionM; // Memory stage instruction caused a fault
logic HPTWInstrAccessFaultM; // Hardware page table access fault while fetching instruction PTE
logic BreakpointFaultM, EcallFaultM; // breakpoint and Ecall traps should retire
logic wfiW;
@ -122,7 +122,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
.STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
// decode privileged instructions
privdec #(P) pmd(.clk, .reset, .StallM, .StallW, .FlushW, .InstrM(InstrM[31:15]),
privdec #(P) pmd(.clk, .reset, .StallW, .FlushW, .InstrM(InstrM[31:15]),
.PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM,
.PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM,
.EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .wfiW, .sfencevmaM);
@ -130,7 +130,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
// Control and Status Registers
csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
.InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, .PC2NextF,
.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM,
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,

View File

@ -68,11 +68,10 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
// Watermark signals - TransmitReadMark = ip[0], ReceiveWriteMark = ip[1]
logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark;
logic TransmitFIFOWriteFull, TransmitFIFOReadEmpty;
logic TransmitFIFOReadIncrement;
logic TransmitFIFOWriteIncrement;
logic ReceiveFIFOReadIncrement;
logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty;
logic [7:0] TransmitFIFOReadData, ReceiveFIFOWriteData;
logic [7:0] TransmitFIFOReadData;
logic [2:0] TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel;
logic [7:0] ReceiveShiftRegEndian; // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
@ -92,7 +91,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
// Frame counting signals
logic [3:0] FrameCount; // Counter for number of frames in transmission
logic [3:0] ReceivePenultimateFrameCount; // Counter
logic ReceivePenultimateFrame; // High when penultimate frame in transmission has been reached
// State fsm signals

View File

@ -158,7 +158,6 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
logic DCacheAccess;
logic ICacheMiss;
logic ICacheAccess;
logic BreakpointFaultM, EcallFaultM;
logic InstrUpdateDAF;
logic BigEndianM;
logic FCvtIntE;
@ -170,7 +169,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
// instruction fetch unit: PC, branch prediction, instruction cache
ifu #(P) ifu(.clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
.InstrValidM, .InstrValidE, .InstrValidD,
.InstrValidE, .InstrValidD,
.BranchD, .BranchE, .JumpD, .JumpE, .ICacheStallF,
// Fetch
.HRDATA, .PCSpillF, .IFUHADDR, .PC2NextF,
@ -270,7 +269,6 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.LSUStallM, .IFUStallF,
.FCvtIntStallD, .FPUStallD,
.DivBusyE, .FDivBusyE,
.EcallFaultM, .BreakpointFaultM,
.wfiM, .IntPendingM,
// Stall & flush outputs
.StallF, .StallD, .StallE, .StallM, .StallW,
@ -298,7 +296,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.PrivilegeModeW, .SATP_REGW,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE, .BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM);
.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE, .wfiM, .IntPendingM, .BigEndianM);
end else begin
assign CSRReadValW = 0;
assign UnalignedPCNextF = PC2NextF;