mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Coverage improvements
This commit is contained in:
David Harris
parent
1b5d254031
commit
69218b4b86
@ -258,5 +258,9 @@ coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0]
|
||||
# EBU
|
||||
####################
|
||||
|
||||
# Exclude EBU Beat Counter because it is only idle when bus has multicycle latency, but rv64gc has single cycle latency
|
||||
coverage exclude -scope /core/ebu/ebu/ebufsmarb/BeatCounter
|
||||
# Exclude EBU Beat Counter flop because it is only idle when bus has multicycle latency, but rv64gc has single cycle latency
|
||||
coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb/BeatCounter/cntrflop
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -148,8 +148,7 @@ module flags import cvw::*; #(parameter cvw_t P) (
|
||||
// Set Inexact flag if the result is diffrent from what would be outputed given infinite precision
|
||||
// - Don't set the underflow flag if an underflowed res isn't outputed
|
||||
assign FpInexact = (Sticky|Guard|Overflow|Round)&~(InfIn|NaNIn|DivByZero|Invalid);
|
||||
//assign FpInexact = (Sticky|Guard|Overflow|Round)&~(InfIn|NaNIn|DivByZero|Invalid|XZero);
|
||||
|
||||
|
||||
// if the res is too small to be represented and not 0
|
||||
// | and if the res is not invalid (outside the integer bounds)
|
||||
// | |
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
///////////////////////////////////////////
|
||||
// ebu.S
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 23 March 2023
|
||||
// Written: David_Harris@hmc.edu 21 January 2024
|
||||
//
|
||||
// Purpose: Test coverage for EBU
|
||||
//
|
||||
@ -24,22 +24,289 @@
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// load code to initalize stack, handle interrupts, terminate
|
||||
|
||||
#include "WALLY-init-lib.h"
|
||||
|
||||
# run-elf.bash find this in project description
|
||||
main:
|
||||
li t5, 0x1
|
||||
slli t5, t5, 62
|
||||
ori t5, t5, 0xF0
|
||||
csrs menvcfg, t5 # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1
|
||||
|
||||
# Test clz with all bits being 0
|
||||
li t0, 0
|
||||
clz t1, t0
|
||||
li t0, -1
|
||||
clz t1, t0
|
||||
li t0, 1
|
||||
clz t1, t0
|
||||
# Page table root address at 0x80010000; SV48
|
||||
li t5, 0x9000000000080010
|
||||
csrw satp, t5
|
||||
|
||||
# Test forwarding from store conditional
|
||||
lr.w t0, 0(a0)
|
||||
sc.w t0, a1, 0(a0)
|
||||
addi t0, t0, 1
|
||||
# sfence.vma x0, x0
|
||||
|
||||
# switch to supervisor mode
|
||||
li a0, 1
|
||||
ecall
|
||||
|
||||
#
|
||||
|
||||
# Tricky case to cover. I$ miss concurrent with DTLB miss. HPTW has to hit the first
|
||||
# access in the cache and miss a later one. Trigger this by doing a load that touches
|
||||
# a page not in the DTLB but where the top-level PTE is already there. Has to happen
|
||||
# near the end of the 16-instruction I$ line.
|
||||
#
|
||||
# Condition Coverage for instance /core/ebu/ebu/ebufsmarb --
|
||||
#
|
||||
# File ../src/ebu/ebufsmarb.sv
|
||||
#----------------Focused Condition View-------------------
|
||||
#Line 72 Item 1 ((HREADY & FinalBeatD) & (LSUReq ~& IFUReq))
|
||||
#Condition totals: 2 of 4 input terms covered = 50.00%
|
||||
#
|
||||
# Input Term Covered Reason for no coverage Hint
|
||||
# ----------- -------- ----------------------- --------------
|
||||
# HREADY Y
|
||||
# FinalBeatD Y
|
||||
# LSUReq N '_1' not hit Hit '_1'
|
||||
# IFUReq N No hits Hit '_0' and '_1'
|
||||
#
|
||||
# Rows: Hits FEC Target Non-masking condition(s)
|
||||
# --------- --------- -------------------- -------------------------
|
||||
# Row 1: 2 HREADY_0 ((LSUReq ~& IFUReq) && FinalBeatD)
|
||||
# Row 2: 14 HREADY_1 ((LSUReq ~& IFUReq) && FinalBeatD)
|
||||
# Row 3: 1 FinalBeatD_0 ((LSUReq ~& IFUReq) && HREADY)
|
||||
# Row 4: 14 FinalBeatD_1 ((LSUReq ~& IFUReq) && HREADY)
|
||||
# Row 5: 14 LSUReq_0 ((HREADY & FinalBeatD) && IFUReq)
|
||||
# Row 6: ***0*** LSUReq_1 ((HREADY & FinalBeatD) && IFUReq)
|
||||
# Row 7: ***0*** IFUReq_0 ((HREADY & FinalBeatD) && LSUReq)
|
||||
# Row 8: ***0*** IFUReq_1 ((HREADY & FinalBeatD) && LSUReq)
|
||||
|
||||
|
||||
li a0, 0x80000000
|
||||
li a1, 0x80A00000
|
||||
j label1
|
||||
|
||||
.align 6 # start on multiple of 64 bytes / 16 instruction cache line
|
||||
label1:
|
||||
addi t2, t3, 0x100 # occupy part of cache line
|
||||
sfence.vma # flush tlb
|
||||
lw t0, 0x234(a0) # load to get an entry in the DTLB accessing top-level PTE
|
||||
addi t2, t3, 0x103 # occupy part of cache line
|
||||
addi t2, t3, 0x104 # occupy part of cache line
|
||||
addi t2, t3, 0x105 # occupy part of cache line
|
||||
addi t2, t3, 0x106 # occupy part of cache line
|
||||
addi t2, t3, 0x107 # occupy part of cache line
|
||||
addi t2, t3, 0x108 # occupy part of cache line
|
||||
addi t2, t3, 0x109 # occupy part of cache line
|
||||
addi t2, t3, 0x10A # occupy part of cache line
|
||||
lw t0, 0x234(a1) # trigger DTLB miss
|
||||
addi t2, t3, 0x10C # occupy part of cache line
|
||||
addi t2, t3, 0x10D # occupy part of cache line
|
||||
addi t2, t3, 0x10E # occupy part of cache line
|
||||
addi t2, t3, 0x10F # occupy part of cache line
|
||||
|
||||
# next multiple of 16
|
||||
addi t2, t3, 0x100 # occupy part of cache line
|
||||
sfence.vma # flush tlb
|
||||
lw t0, 0x334(a0) # load to get an entry in the DTLB accessing top-level PTE
|
||||
addi t2, t3, 0x103 # occupy part of cache line
|
||||
addi t2, t3, 0x104 # occupy part of cache line
|
||||
addi t2, t3, 0x105 # occupy part of cache line
|
||||
addi t2, t3, 0x106 # occupy part of cache line
|
||||
addi t2, t3, 0x107 # occupy part of cache line
|
||||
addi t2, t3, 0x108 # occupy part of cache line
|
||||
addi t2, t3, 0x109 # occupy part of cache line
|
||||
addi t2, t3, 0x10A # occupy part of cache line
|
||||
addi t2, t3, 0x10B # occupy part of cache line
|
||||
lw t0, 0x334(a1) # trigger DTLB miss
|
||||
addi t2, t3, 0x10D # occupy part of cache line
|
||||
addi t2, t3, 0x10E # occupy part of cache line
|
||||
addi t2, t3, 0x10F # occupy part of cache line
|
||||
|
||||
# next multiple of 16
|
||||
addi t2, t3, 0x100 # occupy part of cache line
|
||||
sfence.vma # flush tlb
|
||||
lw t0, 0x434(a0) # load to get an entry in the DTLB accessing top-level PTE
|
||||
addi t2, t3, 0x103 # occupy part of cache line
|
||||
addi t2, t3, 0x104 # occupy part of cache line
|
||||
addi t2, t3, 0x105 # occupy part of cache line
|
||||
addi t2, t3, 0x106 # occupy part of cache line
|
||||
addi t2, t3, 0x107 # occupy part of cache line
|
||||
addi t2, t3, 0x108 # occupy part of cache line
|
||||
addi t2, t3, 0x109 # occupy part of cache line
|
||||
addi t2, t3, 0x10A # occupy part of cache line
|
||||
addi t2, t3, 0x10B # occupy part of cache line
|
||||
addi t2, t3, 0x10C # occupy part of cache line
|
||||
lw t0, 0x434(a1) # trigger DTLB miss
|
||||
addi t2, t3, 0x10E # occupy part of cache line
|
||||
addi t2, t3, 0x10F # occupy part of cache line
|
||||
|
||||
# next multiple of 16
|
||||
addi t2, t3, 0x100 # occupy part of cache line
|
||||
sfence.vma # flush tlb
|
||||
lw t0, 0x534(a0) # load to get an entry in the DTLB accessing top-level PTE
|
||||
addi t2, t3, 0x103 # occupy part of cache line
|
||||
addi t2, t3, 0x104 # occupy part of cache line
|
||||
addi t2, t3, 0x105 # occupy part of cache line
|
||||
addi t2, t3, 0x106 # occupy part of cache line
|
||||
addi t2, t3, 0x107 # occupy part of cache line
|
||||
addi t2, t3, 0x108 # occupy part of cache line
|
||||
addi t2, t3, 0x109 # occupy part of cache line
|
||||
addi t2, t3, 0x10A # occupy part of cache line
|
||||
addi t2, t3, 0x10B # occupy part of cache line
|
||||
addi t2, t3, 0x10C # occupy part of cache line
|
||||
addi t2, t3, 0x10D # occupy part of cache line
|
||||
lw t0, 0x534(a1) # trigger DTLB miss
|
||||
addi t2, t3, 0x10F # occupy part of cache line
|
||||
|
||||
# wrap up
|
||||
li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
|
||||
ecall
|
||||
j done
|
||||
|
||||
|
||||
|
||||
.data
|
||||
|
||||
.align 16
|
||||
# root Page table situated at 0x80010000
|
||||
pagetable:
|
||||
.8byte 0x200044C1 # 0x00000000-0x80_00000000: PTE at 0x80011000 C1 dirty, accessed, valid
|
||||
.8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000
|
||||
|
||||
# next page table at 0x80011000
|
||||
.align 12
|
||||
.8byte 0x00000000000010CF # misaligned gigapage at 0x00000000
|
||||
.8byte 0x00000000200058C1 # PTE for pages at 0x40000000
|
||||
.8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000
|
||||
|
||||
|
||||
# Next page table at 0x80012000 for gigapage at 0x80000000
|
||||
.align 12
|
||||
.8byte 0x0000000020004CC1 # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages)
|
||||
.8byte 0x0000000020014CCF # for VA starting at 80200000 (misaligned megapage)
|
||||
.8byte 0x00000000200050C1 # for VA starting at 80400000 (bad PBMT pages)
|
||||
.8byte 0x4000000020004CC1 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0)
|
||||
.8byte 0x00000000200054C1 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz)
|
||||
.8byte 0x00000000200058C1 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000)
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
|
||||
# Leaf page table at 0x80013000 with NAPOT pages
|
||||
.align 12
|
||||
#80000000
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
|
||||
.8byte 0x800000002000E0CF
|
||||
.8byte 0x800000002000E0CF
|
||||
.8byte 0x800000002000E0CF
|
||||
.8byte 0x800000002000E0CF
|
||||
|
||||
.8byte 0x800000002000E0CF
|
||||
.8byte 0x800000002000E0CF
|
||||
|
||||
# Leaf page table at 0x80014000 with PBMT pages
|
||||
.align 12
|
||||
#80400000
|
||||
.8byte 0x60000000200020CF # reserved entry
|
||||
|
||||
# Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ
|
||||
.align 12
|
||||
#80800000
|
||||
.8byte 0x00000000200000CF # valid rwx for VA 80800000
|
||||
.8byte 0x00000000200000CB # valid r x for VA 80801000
|
||||
.8byte 0x00000000200000C3 # valid r for VA 80802000
|
||||
.8byte 0x00000000200000C9 # valid x for VA 80803000
|
||||
.8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol)
|
||||
.8byte 0x000000002000000F # valid rwx for VA 80805000 for covering ITLB translate and UpdateDA
|
||||
.8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT
|
||||
|
||||
# Leaf page table at 0x80016000 with NAPOT pages
|
||||
.align 12
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
|
||||
@ -156,6 +156,14 @@ main:
|
||||
.word 0x43007053 // illegal fcvt.d.* (bad Rs2D)
|
||||
.word 0x42207053 // illegal fcvt.d.* (bad Rs2D[1])
|
||||
|
||||
// Test divide by zero with rounding mode toward zero
|
||||
li t0, 1
|
||||
csrw frm, t0 // set rounding mode = 1
|
||||
li t0, 0x3f800000
|
||||
fcvt.s.w ft1, t0
|
||||
fcvt.s.w ft2, zero
|
||||
fdiv.s ft3, ft1, ft2
|
||||
|
||||
# Test floating point convert to integer and using result
|
||||
fcvt.w.s t0, f0
|
||||
add t1, t0, t0
|
||||
|
||||
@ -30,4 +30,7 @@ main:
|
||||
|
||||
sfence.vma x0, x0 // sfence.vma to assert TLBFlush
|
||||
|
||||
li a0, 0x80000001 # misaligned address
|
||||
amoadd.w t0, a0, (a0) # amo access to misaligned address
|
||||
|
||||
j done
|
||||
@ -63,14 +63,7 @@ main:
|
||||
li t0, 0x80200000
|
||||
jalr ra, t0 # jump to misaligned megapage
|
||||
|
||||
# exercise ebufsmarb (not yet providing coverage 1/1/24 DH & RT)
|
||||
li t0, 0x80000000
|
||||
lw t1, 0(t0) # fetch from an address to warm up tlb entries
|
||||
li t0, 0x80A00000
|
||||
lw t1, 0(t0) # trigger TLB miss on a non-first entry
|
||||
jal backandforth
|
||||
|
||||
# exercise malformed PBMT pages
|
||||
# exercise malformed PBMT pages
|
||||
|
||||
# page has PBMT = 3 (reserved)
|
||||
li t0, 0x80400000
|
||||
|
||||
Loading…
Reference in New Issue
Block a user