David Harris d7b016e8f3 Cleaned up Zicond implementation		2024-01-12 18:12:52 -08:00
..
cache	Cleanup.	2023-12-29 16:18:30 -06:00
ebu	Added partial code for uncached amo operations.	2023-12-29 15:07:20 -06:00
fpu	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
generic	Revert RAM logic to bit change.	2023-12-20 13:10:20 -06:00
hazard	Moved forwarding logic into controller	2023-12-26 21:17:01 -08:00
ieu	Cleaned up Zicond implementation	2024-01-12 18:12:52 -08:00
ifu	Named IFU decomp generate block	2024-01-01 07:37:40 -08:00
lsu	Fixed bug 546. non-leaf non-zero PBMT bit raise page fault.	2024-01-05 17:10:14 -06:00
mdu	turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep	2023-11-17 20:25:24 -08:00
mmu	Fixed typo in declaration in tlbcontrol; escape quoted argument to Verilator; added ulimit to setup so Verilator stack is large enough	2024-01-06 07:11:25 -08:00
privileged	Fixed bug 546. non-leaf non-zero PBMT bit raise page fault.	2024-01-05 17:10:14 -06:00
uncore	Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match	2023-12-21 12:29:37 -08:00
wally	Fixed bug 546. non-leaf non-zero PBMT bit raise page fault.	2024-01-05 17:10:14 -06:00
cvw.sv	Added Zicond support	2024-01-11 07:37:15 -08:00