cvw/src
2024-01-16 17:27:59 -08:00
..
cache Cleanup. 2023-12-29 16:18:30 -06:00
ebu Atomics work correctly without a d cache. 2024-01-16 10:43:20 -06:00
fpu Zfa fli support working for F and D (add fli.sv module) 2024-01-16 17:27:59 -08:00
generic Revert RAM logic to bit change. 2023-12-20 13:10:20 -06:00
hazard Moved forwarding logic into controller 2023-12-26 21:17:01 -08:00
ieu Fixed the zifencei bug (part of issue 405). 2024-01-15 16:02:37 -06:00
ifu Added logic for the non-cache atomics. 2024-01-15 17:47:17 -06:00
lsu Added logic for the non-cache atomics. 2024-01-15 17:47:17 -06:00
mdu turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep 2023-11-17 20:25:24 -08:00
mmu Fixed typo in declaration in tlbcontrol; escape quoted argument to Verilator; added ulimit to setup so Verilator stack is large enough 2024-01-06 07:11:25 -08:00
privileged tests/coverage/tlbmisc.S 2024-01-15 07:16:11 -08:00
uncore Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match 2023-12-21 12:29:37 -08:00
wally Fixed bug 546. non-leaf non-zero PBMT bit raise page fault. 2024-01-05 17:10:14 -06:00
cvw.sv Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int. 2024-01-15 13:24:57 -08:00