Rose Thompson ab68a76e77 LineDirty is either the Victim Way or the Flush way dirty, but never the hitway dirty. CBO instructions require hitway dirty. However we cannot mux hitway dirty into LineDirty wihtout creating a combinational loop so we need a separate port.		2023-11-29 17:58:39 -06:00
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cache	LineDirty is either the Victim Way or the Flush way dirty, but never the hitway dirty. CBO instructions require hitway dirty. However we cannot mux hitway dirty into LineDirty wihtout creating a combinational loop so we need a separate port.	2023-11-29 17:58:39 -06:00
ebu	Extended the abhcacheinterface to zero a cacheline's worth of uncached memory on cbo.zero.	2023-11-27 21:24:30 -06:00
fpu	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
generic	Commented IROM preloading	2023-11-19 19:33:57 -08:00
hazard	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
ieu	Cleaned up redundant ZICBOM/Z_SUPPORTED.	2023-11-29 15:20:49 -06:00
ifu	Extended the abhcacheinterface to zero a cacheline's worth of uncached memory on cbo.zero.	2023-11-27 21:24:30 -06:00
lsu	Additional cleanup.	2023-11-28 23:28:50 -06:00
mdu	turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep	2023-11-17 20:25:24 -08:00
mmu	Updates to tlb to check access permissions for cbo*	2023-11-29 16:20:43 -06:00
privileged	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-21 14:04:02 -08:00
uncore	Simpilified pmachecker for cmo.	2023-11-29 12:26:18 -06:00
wally	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
cvw.sv	Merge pull request #472 from ross144/main	2023-11-14 08:34:06 -08:00