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https://github.com/openhwgroup/cvw
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Simplified IntDivNormShift
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@ -67,7 +67,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
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// Integer div/rem signals
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logic BZeroM; // Denominator is zero
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logic IntDivM; // Integer operation
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logic [P.DIVBLEN:0] nM, mM; // Shift amounts
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logic [P.DIVBLEN:0] mM, IntDivNormShiftM; // Shift amounts
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logic ALTBM, AsM, BsM, W64M; // Special handling for postprocessor
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logic [P.XLEN-1:0] AM; // Original Numerator for postprocessor
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logic ISpecialCaseE; // Integer div/remainder special cases
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@ -77,7 +77,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
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.FmtE, .SqrtE, .XZeroE, .Funct3E, .UeM, .X, .D, .CyclesE,
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// Int-specific
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.ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE,
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.BZeroM, .nM, .mM, .AM,
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.BZeroM, .IntDivNormShiftM, .mM, .AM,
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.IntDivM, .W64M, .ALTBM, .AsM, .BsM);
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fdivsqrtfsm #(P) fdivsqrtfsm( // FSM
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@ -96,6 +96,6 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
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.SqrtE, .Firstun, .SqrtM, .SpecialCaseM,
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.UmM, .WZeroE, .DivStickyM,
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// Int-specific
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.nM, .mM, .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM,
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.IntDivNormShiftM, .mM, .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM,
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.FIntDivResultM);
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endmodule
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@ -67,6 +67,13 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
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P.Q_FMT: Nf = P.Q_NF;
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endcase
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// Cycle logic
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// P.DIVCOPIES = k. P.LOGR = log(R) = r. P.RK = rk.
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// Integer division needs p fractional + r integer result bits
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// FP Division needs at least Nf fractional bits + 2 guard/round bits and one integer digit (LOG R integer bits) = Nf + 2 + r bits
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// FP Sqrt needs at least Nf fractional bits, 2 guard/round bits, and *** shift bits
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// The datapath produces rk bits per cycle, so Cycles = ceil (ResultBits / rk)
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always_comb begin
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if (SqrtE) FPResultBits = Nf + 2 + 1; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 *** unclear why it works with just +1 rather than +2; is it related to DIVCOPIES logic below?
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else FPResultBits = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
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@ -74,7 +81,7 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
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if (P.IDIV_ON_FPU) ResultBits = IntDivE ? IntResultBits : FPResultBits;
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else ResultBits = FPResultBits;
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assign CyclesE = (ResultBits-1)/(P.RK) + 1;
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assign CyclesE = (ResultBits-1)/(P.RK) + 1; // ceil (ResultBits/rk)
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end
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/* verilator lint_on WIDTH */
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@ -37,7 +37,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
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input logic Firstun, SqrtM, SpecialCaseM,
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input logic [P.XLEN-1:0] AM,
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input logic RemOpM, ALTBM, BZeroM, AsM, BsM, W64M,
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input logic [P.DIVBLEN:0] nM, mM,
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input logic [P.DIVBLEN:0] mM, IntDivNormShiftM,
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output logic [P.DIVb:0] UmM, // result significand
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output logic WZeroE,
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output logic DivStickyM,
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@ -111,7 +111,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
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// Select quotient or remainder and do normalization shift
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localparam DIVa = (P.DIVb+1-P.XLEN); // used for idiv on fpu: Shift residual right by b - (XLEN-1) to put remainder in lsbs of integer result
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mux2 #(P.DIVBLEN+1) normshiftmux(((P.DIVBLEN+1)'(P.DIVb) - (nM * (P.DIVBLEN+1)'(P.LOGR))), (mM + (P.DIVBLEN+1)'(DIVa)), RemOpM, NormShiftM);
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mux2 #(P.DIVBLEN+1) normshiftmux(IntDivNormShiftM, (mM + (P.DIVBLEN+1)'(DIVa)), RemOpM, NormShiftM);
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mux2 #(P.DIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
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assign PreIntResultM = $signed(PreResultM >>> NormShiftM);
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@ -42,7 +42,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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input logic IntDivE, W64E,
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output logic ISpecialCaseE,
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output logic [P.DURLEN-1:0] CyclesE,
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output logic [P.DIVBLEN:0] nM, mM,
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output logic [P.DIVBLEN:0] mM, IntDivNormShiftM,
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output logic ALTBM, IntDivM, W64M,
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output logic AsM, BsM, BZeroM,
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output logic [P.XLEN-1:0] AM
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@ -53,7 +53,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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logic [P.DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
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logic [P.NE+1:0] UeE; // Result Exponent (FP only)
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logic [P.DIVb:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input
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logic [P.DIVBLEN:0] mE, nE, ell; // Leading zeros of inputs
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logic [P.DIVBLEN:0] mE, ell; // Leading zeros of inputs
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logic [P.DIVBLEN:0] IntResultBits; // bits in integer result
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logic NumerZeroE; // Numerator is zero (X or A)
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logic AZeroE, BZeroE; // A or B is Zero for integer division
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@ -126,27 +126,21 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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mux2 #(P.DIVBLEN+1) pmux(ZeroDiff, '0, ALTBE, p);
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/* verilator lint_off WIDTH */
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assign IntResultBits = P.LOGR + p; // Total number of result bits (r integer bits plus p fractional bits)
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assign IntResultBits = P.LOGR + p; // Total number of result bits (r integer bits plus p fractional bits)
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/* verilator lint_on WIDTH */
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// Integer special cases (terminate immediately)
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assign ISpecialCaseE = BZeroE | ALTBE;
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// calculate number of fractional digits nE and right shift amount RightShiftX to complete in discrete number of steps
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// calculate right shift amount RightShiftX to complete in discrete number of steps
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if (P.LOGRK > 0) begin // more than 1 bit per cycle
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logic [P.LOGRK-1:0] IntTrunc, RightShiftX;
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logic [P.DIVBLEN:0] IntSteps;
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/* verilator lint_off WIDTH */
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// n = k*ceil((r+p)/rk) - 1
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assign IntTrunc = IntResultBits % P.RK; // Truncation check for ceiling operator
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assign IntSteps = (IntResultBits >> P.LOGRK) + |IntTrunc; // Number of steps for int div
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assign nE = (IntSteps * P.DIVCOPIES) - 1; // Fractional digits = total digits - 1 integer digit
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/* verilator lint_offf WIDTH */
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assign RightShiftX = P.RK - 1 - ((IntResultBits - 1) % P.RK); // Right shift amount
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assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in nE steps
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assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in n steps
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/* verilator lint_on WIDTH */
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end else begin // radix 2 1 copy doesn't require shifting
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assign nE = p;
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assign DivXShifted = DivX;
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end
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end else begin
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@ -199,17 +193,22 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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fdivsqrtcycles #(P) cyclecalc(.FmtE, .SqrtE, .IntDivE, .IntResultBits, .CyclesE);
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if (P.IDIV_ON_FPU) begin:intpipelineregs
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logic [P.DIVBLEN:0] IntDivNormShiftE;
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/* verilator lint_off WIDTH */
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assign IntDivNormShiftE = P.DIVb - (CyclesE * P.RK - P.LOGR); // b - rn, used for integer normalization right shift. rn = Cycles * r * k - r ***explain
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/* verilator lint_on WIDTH */
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// pipeline registers
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flopen #(1) mdureg(clk, IFDivStartE, IntDivE, IntDivM);
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flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM);
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flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
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flopen #(1) asignreg(clk, IFDivStartE, AsE, AsM);
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flopen #(1) bsignreg(clk, IFDivStartE, BsE, BsM);
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flopen #(P.DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM);
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flopen #(P.DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
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flopen #(P.XLEN) srcareg(clk, IFDivStartE, AE, AM);
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flopen #(1) mdureg(clk, IFDivStartE, IntDivE, IntDivM);
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flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM);
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flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
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flopen #(1) asignreg(clk, IFDivStartE, AsE, AsM);
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flopen #(1) bsignreg(clk, IFDivStartE, BsE, BsM);
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flopen #(P.DIVBLEN+1) nsreg(clk, IFDivStartE, IntDivNormShiftE, IntDivNormShiftM);
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flopen #(P.DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
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flopen #(P.XLEN) srcareg(clk, IFDivStartE, AE, AM);
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if (P.XLEN==64)
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flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M);
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flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M);
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end
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endmodule
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