Rose Thompson 482529394a Fixed some of the uncached ifu bugs.		2023-12-29 09:53:22 -06:00
..
cache	Added parameter for cache's SRAM length.	2023-12-18 12:50:49 -06:00
ebu	Extended the abhcacheinterface to zero a cacheline's worth of uncached memory on cbo.zero.	2023-11-27 21:24:30 -06:00
fpu	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
generic	Revert RAM logic to bit change.	2023-12-20 13:10:20 -06:00
hazard	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
ieu	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-12-15 19:27:10 -08:00
ifu	Fixed some of the uncached ifu bugs.	2023-12-29 09:53:22 -06:00
lsu	Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match	2023-12-14 15:32:36 -08:00
mdu	turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep	2023-11-17 20:25:24 -08:00
mmu	Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match	2023-12-21 12:29:37 -08:00
privileged	Moved UnalignedPCNextF mux into IFU	2023-12-20 16:18:31 -08:00
uncore	Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match	2023-12-21 12:29:37 -08:00
wally	Moved UnalignedPCNextF mux into IFU	2023-12-20 16:18:31 -08:00
cvw.sv	Added parameter for cache's SRAM length.	2023-12-18 12:50:49 -06:00