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https://github.com/openhwgroup/cvw
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Simplified cycle count logic
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@ -30,12 +30,12 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
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input logic [P.FMTBITS-1:0] FmtE,
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input logic SqrtE,
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input logic IntDivE,
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input logic [P.DIVBLEN:0] nE,
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input logic [P.DIVBLEN:0] IntResultBits,
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output logic [P.DURLEN-1:0] CyclesE
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);
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logic [P.DURLEN+1:0] Nf, fbits; // number of fractional bits
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logic [P.DURLEN-1:0] fpcycles; // number of cycles for floating-point operation
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logic [P.DURLEN+1:0] Nf, FPResultBits; // number of fractional bits
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logic [P.DIVBLEN:0] ResultBits; // number of result bits;
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// DIVN = P.NF+3
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// NS = NF + 1
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@ -68,13 +68,13 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
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endcase
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always_comb begin
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if (SqrtE) fbits = Nf + 2 + 1; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 *** unclear why it works with just +1; is it related to DIVCOPIES logic below?
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// if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
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else fbits = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
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assign fpcycles = (fbits-1)/(P.RK) + 1;
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if (SqrtE) FPResultBits = Nf + 2 + 1; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 *** unclear why it works with just +1 rather than +2; is it related to DIVCOPIES logic below?
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else FPResultBits = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
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if (P.IDIV_ON_FPU) CyclesE = IntDivE ? ((nE + 1)/P.DIVCOPIES) : fpcycles;
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else CyclesE = fpcycles;
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if (P.IDIV_ON_FPU) ResultBits = IntDivE ? IntResultBits : FPResultBits;
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else ResultBits = FPResultBits;
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assign CyclesE = (ResultBits-1)/(P.RK) + 1;
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end
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/* verilator lint_on WIDTH */
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@ -54,6 +54,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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logic [P.NE+1:0] UeE; // Result Exponent (FP only)
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logic [P.DIVb:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input
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logic [P.DIVBLEN:0] mE, nE, ell; // Leading zeros of inputs
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logic [P.DIVBLEN:0] IntResultBits; // bits in integer result
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logic NumerZeroE; // Numerator is zero (X or A)
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logic AZeroE, BZeroE; // A or B is Zero for integer division
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logic SignedDivE; // signed division
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@ -122,7 +123,11 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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// calculate number of fractional bits p
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assign ZeroDiff = mE - ell; // Difference in number of leading zeros
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assign ALTBE = ZeroDiff[P.DIVBLEN]; // A less than B (A has more leading zeros)
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mux2 #(P.DIVBLEN+1) pmux(ZeroDiff, '0, ALTBE, p);
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mux2 #(P.DIVBLEN+1) pmux(ZeroDiff, '0, ALTBE, p);
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/* verilator lint_off WIDTH */
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assign IntResultBits = P.LOGR + p; // Total number of result bits (r integer bits plus p fractional bits)
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/* verilator lint_on WIDTH */
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// Integer special cases (terminate immediately)
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assign ISpecialCaseE = BZeroE | ALTBE;
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@ -131,15 +136,14 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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if (P.LOGRK > 0) begin // more than 1 bit per cycle
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logic [P.LOGRK-1:0] IntTrunc, RightShiftX;
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logic [P.DIVBLEN:0] TotalIntBits, IntSteps;
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logic [P.DIVBLEN:0] IntSteps;
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/* verilator lint_off WIDTH */
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// n = k*ceil((r+p)/rk) - 1
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assign TotalIntBits = P.LOGR + p; // Total number of result bits (r integer bits plus p fractional bits)
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assign IntTrunc = TotalIntBits % P.RK; // Truncation check for ceiling operator
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assign IntSteps = (TotalIntBits >> P.LOGRK) + |IntTrunc; // Number of steps for int div
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assign nE = (IntSteps * P.DIVCOPIES) - 1; // Fractional digits = total digits - 1 integer digit
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assign RightShiftX = P.RK - 1 - ((TotalIntBits - 1) % P.RK); // Right shift amount
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assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in nE steps
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assign IntTrunc = IntResultBits % P.RK; // Truncation check for ceiling operator
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assign IntSteps = (IntResultBits >> P.LOGRK) + |IntTrunc; // Number of steps for int div
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assign nE = (IntSteps * P.DIVCOPIES) - 1; // Fractional digits = total digits - 1 integer digit
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assign RightShiftX = P.RK - 1 - ((IntResultBits - 1) % P.RK); // Right shift amount
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assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in nE steps
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/* verilator lint_on WIDTH */
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end else begin // radix 2 1 copy doesn't require shifting
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assign nE = p;
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@ -192,7 +196,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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flopen #(P.NE+2) expreg(clk, IFDivStartE, UeE, UeM);
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// Number of FSM cycles (to FSM)
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fdivsqrtcycles #(P) cyclecalc(.FmtE, .SqrtE, .IntDivE, .nE, .CyclesE);
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fdivsqrtcycles #(P) cyclecalc(.FmtE, .SqrtE, .IntDivE, .IntResultBits, .CyclesE);
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if (P.IDIV_ON_FPU) begin:intpipelineregs
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// pipeline registers
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