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Finished LSU tlbcontrol coverage tests

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This commit is contained in:
David Harris 2024-01-02 10:16:20 -08:00
parent d229dc06ee
commit 680a014876
3 changed files with 21 additions and 6 deletions
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2
src/lsu/lsu.sv
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@ -308,7 +308,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
if(P.ZICBOZ_SUPPORTED) begin
assign BusCMOZero = CMOpM[3] & ~CacheableM;
assign CacheCMOpM = CacheableM ? CMOpM : '0;
assign CacheCMOpM = (CacheableM & ~SelHPTW) ? CMOpM : '0;
assign BusAtomic = AtomicM[1] & ~CacheableM;
end else begin
assign BusCMOZero = '0;

2
src/mmu/hptw.sv
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@ -262,7 +262,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
// 2. If the store would generate an exception don't store to dcache but still write the TLB. When we go back
// to LEAF then the PMA/P. Wait this does not work. The PMA/P won't be looking a the address in the table, but
// rather than physical address of the translated instruction/data. So we must generate the exception.
// *** DH 1/1/24 another bug: when the NAPOT bits (PTE[62:61]) are nonzero on a nonleaf PTE, the walker should make a page fault
// *** DH 1/1/24 another bug: when the NAPOT bits (PTE[62:61]) are nonzero on a nonleaf PTE, the walker should make a page fault (Issue 546)
flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState);
always_comb
case (WalkerState)

23
tests/coverage/tlbmisc.S
View File

@ -59,6 +59,12 @@ main:
li t0, 0x80200000
jalr ra, t0 # jump to misaligned megapage
# exercise ebufsmarb
li t0, 0x80000000
lw t1, 0(t0) # fetch from an address to warm up tlb entries
li t0, 0x80A00000
lw t1, 0(t0) # trigger TLB miss on a non-first entry
jal backandforth
# exercise malformed PBMT pages
@ -91,6 +97,9 @@ main:
li t0, 0x80803000
cbo.zero (t0)
cbo.clean (t0)
li t0, 0x80804000
cbo.zero (t0)
cbo.clean (t0)
# set mstatus.MXR
li a0, 3
@ -114,6 +123,9 @@ main:
li t0, 0x80803000
cbo.zero (t0)
cbo.clean (t0)
li t0, 0x80804000
cbo.zero (t0)
cbo.clean (t0)
# clear mstatus.MXR
li a0, 3
@ -130,6 +142,8 @@ main:
ecall
j done
backandforth:
ret
changetoipfhandler:
li a0, 3
@ -197,7 +211,7 @@ pagetable:
.8byte 0x00000000200050C1 # for VA starting at 80400000 (bad PBMT pages)
.8byte 0x4000000020004CC1 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0)
.8byte 0x00000000200054C1 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz)
.8byte 0x0000000020004CC1
.8byte 0x0000000020004CC1 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000)
.8byte 0x0000000020004CC1
.8byte 0x0000000020004CC1
.8byte 0x0000000020004CC1
@ -311,8 +325,9 @@ pagetable:
.align 12
#80800000
.8byte 0x00000000200000CF # valid rwx for VA 80800000
.8byte 0x00000000200000CF # valid r x for VA 80801000
.8byte 0x00000000200000CF # valid r for VA 80802000
.8byte 0x00000000200000CF # valid x for CA 80003000
.8byte 0x00000000200000CB # valid r x for VA 80801000
.8byte 0x00000000200000C3 # valid r for VA 80802000
.8byte 0x00000000200000C5 # valid x for VA 80803000
.8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol)