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https://github.com/openhwgroup/cvw
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Temporary fix of InstrM to prevent testbench hanging
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09aebbf252
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@ -386,22 +386,22 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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assign BranchMisalignedFaultE = (IEUAdrE[1] & ~P.COMPRESSED_SUPPORTED) & PCSrcE;
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flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
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// Instruction and PC pipeline registers
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// Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0.
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// Instruction and PC pipeline registers flush to NOP, not zero
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mux2 #(32) FlushInstrEMux(InstrD, nop, FlushE, NextInstrD);
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mux2 #(32) FlushInstrMMux(InstrE, nop, FlushM, NextInstrE);
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flopenr #(32) InstrEReg(clk, reset, ~StallE, NextInstrD, InstrE);
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flopenr #(P.XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
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// InstrM is only needed with CSRs or atomic operations
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if (P.ZICSR_SUPPORTED | P.A_SUPPORTED)
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if (P.ZICSR_SUPPORTED | P.A_SUPPORTED | 1)
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flopenr #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
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else assign InstrM = 0;
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// PCM is only needed with CSRs or branch prediction
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if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED)
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flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
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else assign PCM = 0;
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// If compressed instructions are supported, increment PCLink by 2 or 4 for a jal. Otherwise, just by 4
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if (P.COMPRESSED_SUPPORTED) begin
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logic CompressedD; // instruction is compressed
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flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
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@ -411,9 +411,9 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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assign CompressedE = 0;
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assign PCLinkE = PCE + 'd4;
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end
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// pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception
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if (P.ZICSR_SUPPORTED & P.COMPRESSED_SUPPORTED) begin
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if (P.ZICSR_SUPPORTED & P.COMPRESSED_SUPPORTED | 1) begin
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logic CompressedM; // instruction is compressed
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flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
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flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
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