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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev

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This commit is contained in:
David Harris 2023-11-21 14:04:02 -08:00
commit 3f3c20a38f
12 changed files with 171 additions and 80 deletions
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2
config/buildroot/config.vh
View File

@ -100,7 +100,7 @@ localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b1;
localparam UNCORE_RAM_SUPPORTED = 1'b1;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h0FFFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b1;
localparam EXT_MEM_SUPPORTED = 1'b0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;

115
linux/buildroot-config-src/buildroot-2023.05.1/linux.config
View File

@ -2,7 +2,7 @@
# Automatically generated file; DO NOT EDIT.
# Linux/riscv 6.6.0 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2023.05.3) 12.3.0"
CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2023.05.3-dirty) 12.3.0"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=120300
CONFIG_CLANG_VERSION=0
@ -131,15 +131,14 @@ CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="${BR_BINARIES_DIR}/rootfs.cpio"
CONFIG_INITRAMFS_ROOT_UID=0
CONFIG_INITRAMFS_ROOT_GID=0
CONFIG_RD_GZIP=y
# CONFIG_RD_GZIP is not set
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_LZ4 is not set
# CONFIG_RD_ZSTD is not set
CONFIG_INITRAMFS_COMPRESSION_GZIP=y
# CONFIG_INITRAMFS_COMPRESSION_NONE is not set
CONFIG_INITRAMFS_COMPRESSION_NONE=y
# CONFIG_BOOT_CONFIG is not set
CONFIG_INITRAMFS_PRESERVE_MTIME=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
@ -261,8 +260,7 @@ CONFIG_RISCV_ISA_C=y
CONFIG_RISCV_ISA_SVNAPOT=y
CONFIG_RISCV_ISA_SVPBMT=y
CONFIG_TOOLCHAIN_HAS_V=y
CONFIG_RISCV_ISA_V=y
CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y
# CONFIG_RISCV_ISA_V is not set
CONFIG_RISCV_ISA_ZICBOM=y
CONFIG_RISCV_ISA_ZICBOZ=y
CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
@ -305,17 +303,8 @@ CONFIG_PORTABLE=y
#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
CONFIG_PM_SLEEP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_CLK=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
# CONFIG_SUSPEND is not set
# CONFIG_PM is not set
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options
@ -387,6 +376,7 @@ CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_HUGE_VMALLOC=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_WANT_PMD_MKWRITE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
@ -418,7 +408,6 @@ CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
CONFIG_DYNAMIC_SIGFRAME=y
#
# GCOV-based kernel profiling
@ -467,7 +456,6 @@ CONFIG_EFI_PARTITION=y
# end of Partition Types
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
#
# IO Schedulers
@ -483,7 +471,6 @@ CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_MMIOWB=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
CONFIG_FREEZER=y
#
# Executable file formats
@ -532,18 +519,23 @@ CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y
CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_WANTS_THP_SWAP=y
# CONFIG_TRANSPARENT_HUGEPAGE is not set
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
CONFIG_THP_SWAP=y
# CONFIG_READ_ONLY_THP_FOR_FS is not set
CONFIG_NEED_PER_CPU_KM=y
# CONFIG_CMA is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ZONE_DMA32=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_TEST is not set
# CONFIG_DMAPOOL_TEST is not set
@ -589,7 +581,6 @@ CONFIG_FW_LOADER=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_FW_LOADER_USER_HELPER is not set
# CONFIG_FW_LOADER_COMPRESS is not set
CONFIG_FW_CACHE=y
# CONFIG_FW_UPLOAD is not set
# end of Firmware loader
@ -607,6 +598,7 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y
#
# Bus devices
#
# CONFIG_MOXTET is not set
# CONFIG_MHI_BUS is not set
# CONFIG_MHI_BUS_EP is not set
# end of Bus devices
@ -687,8 +679,10 @@ CONFIG_BLK_DEV=y
#
# Misc devices
#
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
# CONFIG_SRAM is not set
# CONFIG_XILINX_SDFEC is not set
# CONFIG_OPEN_DICE is not set
@ -698,7 +692,9 @@ CONFIG_BLK_DEV=y
#
# EEPROM support
#
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_EEPROM_93XX46 is not set
# end of EEPROM support
#
@ -706,6 +702,8 @@ CONFIG_BLK_DEV=y
#
# end of Texas Instruments shared transport line discipline
# CONFIG_SENSORS_LIS3_SPI is not set
#
# Altera FPGA firmware download module (requires I2C)
#
@ -767,7 +765,6 @@ CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
@ -796,12 +793,15 @@ CONFIG_SERIAL_OF_PLATFORM=y
# Non-8250 serial port support
#
# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_SERIAL_SIFIVE=y
CONFIG_SERIAL_SIFIVE_CONSOLE=y
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_XILINX_PS_UART is not set
@ -839,7 +839,43 @@ CONFIG_DEVPORT=y
# end of I2C support
# CONFIG_I3C is not set
# CONFIG_SPI is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
# CONFIG_SPI_MEM is not set
#
# SPI Master Controller Drivers
#
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_MICROCHIP_CORE is not set
# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
# CONFIG_SPI_OC_TINY is not set
CONFIG_SPI_SIFIVE=y
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_SPI_AMD is not set
#
# SPI Multiplexer support
#
# CONFIG_SPI_MUX is not set
#
# SPI Protocol Masters
#
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_LOOPBACK_TEST is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_SLAVE is not set
# CONFIG_SPMI is not set
# CONFIG_HSI is not set
# CONFIG_PPS is not set
@ -887,6 +923,17 @@ CONFIG_GPIO_SIFIVE=y
#
# end of MFD GPIO expanders
#
# SPI GPIO expanders
#
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# end of SPI GPIO expanders
#
# Virtual GPIO drivers
#
@ -914,13 +961,26 @@ CONFIG_BCMA_POSSIBLE=y
# CONFIG_MFD_ATMEL_FLEXCOM is not set
# CONFIG_MFD_ATMEL_HLCDC is not set
# CONFIG_MFD_MADERA is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_OCELOT is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_RK8XX_SPI is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_STMPE is not set
# CONFIG_MFD_SYSCON is not set
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_TPS6594_SPI is not set
# CONFIG_MFD_TQMX86 is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MFD_INTEL_M10_BMC_SPI is not set
# CONFIG_MFD_RSMU_SPI is not set
# end of Multifunction device drivers
# CONFIG_REGULATOR is not set
@ -982,6 +1042,7 @@ CONFIG_MMC_BLOCK_MINORS=8
#
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_DW is not set
# CONFIG_MMC_USDHI6ROL0 is not set
# CONFIG_MMC_CQHCI is not set
@ -1021,6 +1082,7 @@ CONFIG_VIRTIO=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
# CONFIG_LMK04832 is not set
# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
# CONFIG_XILINX_VCU is not set
@ -1484,10 +1546,9 @@ CONFIG_CRC32_SLICEBY8=y
# CONFIG_LIBCRC32C is not set
# CONFIG_CRC8 is not set
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_ZLIB_INFLATE=y
# CONFIG_XZ_DEC is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_XARRAY_MULTI=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y

18
linux/buildroot-config-src/buildroot-2023.05.1/main.config
View File

@ -844,7 +844,14 @@ BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y
# ogre needs X11 and an OpenGL provider
#
# BR2_PACKAGE_PSPLASH is not set
# BR2_PACKAGE_SDL is not set
BR2_PACKAGE_SDL=y
BR2_PACKAGE_SDL_FBCON=y
# BR2_PACKAGE_SDL_GFX is not set
# BR2_PACKAGE_SDL_IMAGE is not set
# BR2_PACKAGE_SDL_MIXER is not set
# BR2_PACKAGE_SDL_NET is not set
# BR2_PACKAGE_SDL_SOUND is not set
# BR2_PACKAGE_SDL_TTF is not set
# BR2_PACKAGE_SDL2 is not set
# BR2_PACKAGE_VULKAN_HEADERS is not set
@ -2529,13 +2536,14 @@ BR2_TARGET_ROOTFS_INITRAMFS=y
# BR2_TARGET_BEAGLEV_DDRINIT is not set
# BR2_TARGET_BEAGLEV_SECONDBOOT is not set
BR2_TARGET_OPENSBI=y
BR2_TARGET_OPENSBI_LATEST_VERSION=y
# BR2_TARGET_OPENSBI_CUSTOM_VERSION is not set
# BR2_TARGET_OPENSBI_LATEST_VERSION is not set
BR2_TARGET_OPENSBI_CUSTOM_VERSION=y
# BR2_TARGET_OPENSBI_CUSTOM_TARBALL is not set
# BR2_TARGET_OPENSBI_CUSTOM_GIT is not set
BR2_TARGET_OPENSBI_VERSION="1.2"
BR2_TARGET_OPENSBI_CUSTOM_VERSION_VALUE="1.3"
BR2_TARGET_OPENSBI_VERSION="1.3"
BR2_TARGET_OPENSBI_PLAT="generic"
BR2_TARGET_OPENSBI_INSTALL_DYNAMIC_IMG=y
# BR2_TARGET_OPENSBI_INSTALL_DYNAMIC_IMG is not set
BR2_TARGET_OPENSBI_INSTALL_JUMP_IMG=y
# BR2_TARGET_OPENSBI_INSTALL_PAYLOAD_IMG is not set
# BR2_TARGET_OPENSBI_LINUX_PAYLOAD is not set

9
linux/testvector-generation/genInitMem.sh
View File

@ -1,13 +1,14 @@
#!/bin/bash
tcpPort=1235
imageDir=/home/jpease/repos/buildroot3/output/images
tvDir=linux-testvectors
imageDir=$RISCV/buildroot/output/images
tvDir=$RISCV/linux-testvectors
rawRamFile="$tvDir/ramGDB.bin"
ramFile="$tvDir/ram.bin"
rawBootmemFile="$tvDir/bootmemGDB.bin"
bootmemFile="$tvDir/bootmem.bin"
rawUntrimmedBootmemFile="$tvDir/untrimmedBootmemFileGDB.bin"
untrimmedBootmemFile="$tvDir/untrimmedBootmemFile.bin"
DEVICE_TREE=../devicetree/wally-virt.dtb
read -p "Warning: running this script will overwrite the contents of:
* $rawRamFile
@ -36,7 +37,7 @@ then
echo "Launching QEMU in replay mode!"
(qemu-system-riscv64 \
-M virt -dtb /home/jpease/repos/buildroot3/output/images/wally-artya7.dtb \
-M virt -m 256M -dtb $DEVICE_TREE \
-nographic \
-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
-gdb tcp::$tcpPort -S) \
@ -53,7 +54,7 @@ then
-ex "printf \"Warning - please verify that the second half of $rawUntrimmedBootmemFile is all 0s\n\"" \
-ex "dump binary memory $rawUntrimmedBootmemFile 0x1000 0x2fff" \
-ex "printf \"Creating $rawRamFile\n\"" \
-ex "dump binary memory $rawRamFile 0x80000000 0x87ffffff" \
-ex "dump binary memory $rawRamFile 0x80000000 0x8fffffff" \
-ex "kill" \
-ex "q"

3
linux/testvector-generation/genRecording.sh
View File

@ -2,6 +2,7 @@
imageDir=$RISCV/buildroot/output/images
tvDir=$RISCV/linux-testvectors
recordFile="$tvDir/all.qemu"
DEVICE_TREE=../devicetree/wally-virt.dtb
read -p "Warning: running this script will overwrite $recordFile
Would you like to proceed? (y/n) " -n 1 -r
@ -24,7 +25,7 @@ then
echo "Launching QEMU in record mode!"
qemu-system-riscv64 \
-M virt -dtb $imageDir/wally-virt.dtb \
-M virt -m 256M -dtb $DEVICE_TREE \
-nographic \
-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=record,rrfile=$recordFile

3
linux/testvector-generation/genTrace.sh
View File

@ -6,6 +6,7 @@ recordFile="$tvDir/all.qemu"
traceFile="$tvDir/all.txt"
trapsFile="$tvDir/traps.txt"
interruptsFile="$tvDir/interrupts.txt"
DEVICE_TREE=../devicetree/wally-virt.dtb
read -p "Warning: running this script will overwrite the contents of:
* $traceFile
@ -36,7 +37,7 @@ then
# QEMU Simulation
echo "Launching QEMU in replay mode!"
(qemu-system-riscv64 \
-M virt -dtb $imageDir/wally-virt.dtb \
-M virt -m 256M -dtb $DEVICE_TREE \
-nographic \
-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=replay,rrfile=$recordFile \

2
sim/imperas.ic
View File

@ -8,6 +8,8 @@
--override cpu/user_version=20191213
# arch
--override cpu/mimpid=0x100
--override cpu/mvendorid=0x602
--override cpu/marchid=0x24
--override refRoot/cpu/tvec_align=64
# bit manipulation

6
src/cache/cache.sv vendored
View File

@ -88,7 +88,7 @@ module cache import cvw::*; #(parameter cvw_t P,
logic FlushAdrFlag, FlushWayFlag;
logic [NUMWAYS-1:0] FlushWay, NextFlushWay;
logic FlushWayCntEn;
logic SelBothWriteback;
logic SelWriteback;
logic LRUWriteEn;
logic SelFlush;
logic ResetOrFlushCntRst;
@ -156,7 +156,7 @@ module cache import cvw::*; #(parameter cvw_t P,
mux3 #(PA_BITS) CacheBusAdrMux(.d0({PAdr[PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
.d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
.d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}),
.s({SelFlush, SelBothWriteback}), .y(CacheBusAdr));
.s({SelFlush, SelWriteback}), .y(CacheBusAdr));
/////////////////////////////////////////////////////////////////////////////////////////////
// Write Path
@ -227,7 +227,7 @@ module cache import cvw::*; #(parameter cvw_t P,
.FlushStage, .CacheRW, .Stall,
.CacheHit, .LineDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdr, .SelWay,
.ClearDirty, .SetDirty, .SetValid, .ClearValid, .ZeroCacheLine, .SelBothWriteback, .SelFlush,
.ClearDirty, .SetDirty, .SetValid, .ClearValid, .ZeroCacheLine, .SelWriteback, .SelFlush,
.FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
.FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,
.InvalidateCache, .CMOp, .CacheEn, .LRUWriteEn);

55
src/cache/cachefsm.sv vendored
View File

@ -59,7 +59,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
output logic SetDirty, // Set the dirty bit in the selected way and set
output logic ClearDirty, // Clear the dirty bit in the selected way and set
output logic ZeroCacheLine, // Write zeros to all bytes of cacheline
output logic SelBothWriteback, // Overrides cached tag check to select a specific way and set for writeback
output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback
output logic LRUWriteEn, // Update the LRU state
output logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
output logic SelWay, // Controls which way to select a way data and tag, 00 = hitway, 10 = victimway, 11 = flushway
@ -75,10 +75,9 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
logic AnyMiss;
logic FlushFlag;
logic CMOWritebackHit;
logic CMOWriteback;
logic CMOZeroNoEviction;
logic CMOZeroEviction;
logic SelWriteback; // Overrides cached tag check to select a specific way and set for writeback
logic SelCMOWriteback; // Overrides cached tag check to select a specific way and set for writeback for both data and tag
typedef enum logic [3:0]{STATE_READY, // hit states
// miss states
@ -88,10 +87,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
STATE_READ_HOLD, // required for back to back reads. structural hazard on writting SRAM
// flush cache
STATE_FLUSH,
STATE_FLUSH_WRITEBACK,
// CMO states
STATE_CMO_WRITEBACK,
STATE_CMO_DONE
STATE_FLUSH_WRITEBACK
} statetype;
statetype CurrState, NextState;
@ -102,6 +98,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
assign CMOWritebackHit = (CMOp[1] | CMOp[2]) & CacheHit;
assign CMOZeroNoEviction = CMOp[3] & ~LineDirty; // (hit or miss) with no writeback store zeros now
assign CMOZeroEviction = CMOp[3] & LineDirty; // (hit or miss) with writeback dirty line
assign CMOWriteback = CMOWritebackHit | CMOZeroEviction;
assign FlushFlag = FlushAdrFlag & FlushWayFlag;
@ -124,8 +121,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
STATE_READY: if(InvalidateCache) NextState = STATE_READY; // exclusion-tag: dcache InvalidateCheck
else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH;
else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; // exclusion-tag: icache FETCHStatement
else if(AnyMiss | CMOZeroEviction) NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement
else if(CMOWritebackHit) NextState = STATE_CMO_WRITEBACK;
else if(AnyMiss | CMOWriteback) NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement
else NextState = STATE_READY;
STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE;
else if(CacheBusAck) NextState = STATE_READY;
@ -134,8 +130,9 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD;
else NextState = STATE_READY;
// exclusion-tag-start: icache case
STATE_WRITEBACK: if(CacheBusAck & ~CMOp[3]) NextState = STATE_FETCH;
else if(CacheBusAck) NextState = STATE_CMO_DONE;
STATE_WRITEBACK: if (CacheBusAck & (CMOp[1] | CMOp[2])) NextState = STATE_READ_HOLD;
else if(CacheBusAck & ~CMOp[3]) NextState = STATE_FETCH;
else if(CacheBusAck) NextState = STATE_READ_HOLD;
else NextState = STATE_WRITEBACK;
// eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK;
@ -144,31 +141,25 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH;
else if(CacheBusAck) NextState = STATE_READ_HOLD;
else NextState = STATE_FLUSH_WRITEBACK;
STATE_CMO_WRITEBACK: if(CacheBusAck & (CMOp[1] | CMOp[2])) NextState = STATE_CMO_DONE;
else NextState = STATE_CMO_WRITEBACK;
STATE_CMO_DONE: if(Stall) NextState = STATE_CMO_DONE;
else NextState = STATE_READY;
// exclusion-tag-end: icache case
default: NextState = STATE_READY;
endcase
end
// com back to CPU
assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & (CurrState == STATE_READ_HOLD | CurrState == STATE_CMO_DONE));
assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss | CMOWritebackHit | CMOZeroEviction)) | // exclusion-tag: icache StallStates
assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & (CurrState == STATE_READ_HOLD));
assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss | CMOWriteback)) | // exclusion-tag: icache StallStates
(CurrState == STATE_FETCH) |
(CurrState == STATE_WRITEBACK) |
(CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
(CurrState == STATE_FLUSH) |
(CurrState == STATE_FLUSH_WRITEBACK) |
(CurrState == STATE_CMO_WRITEBACK);
(CurrState == STATE_FLUSH_WRITEBACK);
// write enables internal to cache
assign SetValid = CurrState == STATE_WRITE_LINE |
(P.ZICBOZ_SUPPORTED & CurrState == STATE_READY & CMOZeroNoEviction) |
(P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CacheBusAck & CMOp[3]);
assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0] & CacheHit) |
(CurrState == STATE_CMO_WRITEBACK & CMOp[2] & CacheBusAck));
(CurrState == STATE_WRITEBACK & CMOp[2] & CacheBusAck));
// coverage off -item e 1 -fecexprrow 8
assign LRUWriteEn = (((CurrState == STATE_READY & (AnyHit | CMOZeroNoEviction)) |
(CurrState == STATE_WRITE_LINE)) & ~FlushStage) |
@ -180,19 +171,14 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) | // exclusion-tag: icache ClearDirty
(CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set.
// Flush and eviction controls
(P.ZICBOM_SUPPORTED & CurrState == STATE_CMO_WRITEBACK & (CMOp[1] | CMOp[2]) & CacheBusAck);
assign SelWay = SelWriteback | (CurrState == STATE_WRITE_LINE) |
// This is almost the same as setvalid, but on cachehit we don't want to select
// the nonhit way, but instead want to force this to zero
(P.ZICBOZ_SUPPORTED & CurrState == STATE_READY & CMOZeroNoEviction & ~CacheHit) |
(P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CacheBusAck & CMOp[3]);
(P.ZICBOM_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2]) & CacheBusAck);
assign SelWay = (CurrState == STATE_WRITEBACK & ((~CacheBusAck & ~(CMOp[1] | CMOp[2])) | (P.ZICBOZ_SUPPORTED & CacheBusAck & CMOp[3]))) |
(CurrState == STATE_READY & ((AnyMiss & LineDirty) | (P.ZICBOZ_SUPPORTED & CMOZeroNoEviction & ~CacheHit))) |
(CurrState == STATE_WRITE_LINE);
assign ZeroCacheLine = P.ZICBOZ_SUPPORTED & ((CurrState == STATE_READY & CMOZeroNoEviction) |
(CurrState == STATE_WRITEBACK & (CMOp[3] & CacheBusAck)));
assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
(CurrState == STATE_READY & AnyMiss & LineDirty);
assign SelCMOWriteback = CurrState == STATE_CMO_WRITEBACK;
assign SelBothWriteback = SelWriteback | SelCMOWriteback;
assign SelWriteback = (CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2] | ~CacheBusAck)) |
(CurrState == STATE_READY & AnyMiss & LineDirty);
assign SelFlush = (CurrState == STATE_READY & FlushCache) |
(CurrState == STATE_FLUSH) |
(CurrState == STATE_FLUSH_WRITEBACK);
@ -208,17 +194,16 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
// Bus interface controls
assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | // exclusion-tag: icache CacheBusRCauses
(CurrState == STATE_FETCH & ~CacheBusAck) |
(CurrState == STATE_WRITEBACK & CacheBusAck & ~CMOp[3]);
(CurrState == STATE_WRITEBACK & CacheBusAck & ~(|CMOp));
assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) | // exclusion-tag: icache CacheBusW
(CurrState == STATE_WRITEBACK & ~CacheBusAck) |
(CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck) |
(P.ZICBOM_SUPPORTED & CurrState == STATE_CMO_WRITEBACK & (CMOp[1] | CMOp[2]) & ~CacheBusAck);
(P.ZICBOM_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2]) & ~CacheBusAck);
assign SelAdr = (CurrState == STATE_READY & (CacheRW[0] | AnyMiss | (|CMOp))) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed
(CurrState == STATE_FETCH) |
(CurrState == STATE_WRITEBACK) |
(CurrState == STATE_WRITE_LINE) |
(CurrState == STATE_CMO_WRITEBACK) |
resetDelay;
assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD;
assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache; // exclusion-tag: dcache CacheEn

6
src/privileged/csrm.sv
View File

@ -60,7 +60,7 @@ module csrm import cvw::*; #(parameter cvw_t P) (
// Machine CSRs
localparam MVENDORID = 12'hF11;
localparam MARCHID = 12'hF12;
localparam MARCHID = 12'hF12; // github.com/riscv/riscv-isa-manual/blob/main/marchid.md
localparam MIMPID = 12'hF13;
localparam MHARTID = 12'hF14;
localparam MCONFIGPTR = 12'hF15;
@ -216,8 +216,8 @@ module csrm import cvw::*; #(parameter cvw_t P) (
end
else case (CSRAdrM)
MISA_ADR: CSRMReadValM = MISA_REGW;
MVENDORID: CSRMReadValM = 0;
MARCHID: CSRMReadValM = 0;
MVENDORID: CSRMReadValM = {{(P.XLEN-32){1'b0}}, 32'h0000_0602}; // OpenHW JEDEC
MARCHID: CSRMReadValM = {{(P.XLEN-32){1'b0}}, 32'h24}; // 36 for CV-Wally
MIMPID: CSRMReadValM = {{P.XLEN-12{1'b0}}, 12'h100}; // pipelined implementation
MHARTID: CSRMReadValM = MHARTID_REGW; // hardwired to 0
MCONFIGPTR: CSRMReadValM = 0; // hardwired to 0

1
synthDC/ppa/ppaAnalyze.py
View File

@ -67,6 +67,7 @@ def synthsintocsv():
for oneSynth in allSynths:
module, width, risc, tech, freq = specReg.findall(oneSynth)[1:6]
tech = tech[:-2]
metrics = []
for phrase in [["Path Slack", "qor"], ["Design Area", "qor"], ["100", "power"]]:
bashCommand = 'grep "{}" ' + oneSynth[2:] + "/reports/*{}*"

31
testbench/common/wallyTracer.sv
View File

@ -23,6 +23,7 @@
`define NUM_REGS 32
`define NUM_CSRS 4096
`define STD_LOG 0
`define PRINT_PC_INSTR 0
`define PRINT_MOST 0
`define PRINT_ALL 0
@ -495,8 +496,38 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
integer index2;
string instrWName;
int file;
string LogFile;
if(`STD_LOG) begin
instrNameDecTB NameDecoder(rvvi.insn[0][0], instrWName);
initial begin
LogFile = "logs/InstrTrace.log";
file = $fopen(LogFile, "w");
end
end
always_ff @(posedge clk) begin
if(rvvi.valid[0][0]) begin
if(`STD_LOG) begin
$fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName);
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
if(rvvi.x_wb[0][0][index2]) begin
$fwrite(file, "rf[%02d] = %016x ", index2, rvvi.x_wdata[0][0][index2]);
end
end
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
if(rvvi.f_wb[0][0][index2]) begin
$fwrite(file, "frf[%02d] = %016x ", index2, rvvi.f_wdata[0][0][index2]);
end
end
for(index2 = 0; index2 < `NUM_CSRS; index2 += 1) begin
if(rvvi.csr_wb[0][0][index2]) begin
$fwrite(file, "csr[%03x] = %016x ", index2, rvvi.csr[0][0][index2]);
end
end
$fwrite(file, "\n");
end
if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST))
$display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]);
else if(`PRINT_MOST & !`PRINT_ALL)