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https://github.com/openhwgroup/cvw
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Reverted dtim to use store delay stall, but only (load after store).
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@ -458,12 +458,15 @@ module controller import cvw::*; #(parameter cvw_t P) (
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assign MDUStallD = MDUE & MatchDE; // Int mult/div is at least two cycle latency, even when coming from the FDIV
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assign CSRRdStallD = CSRReadE & MatchDE;
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logic StoreStallD;
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// atomic operations are also detected as MemRWE[1] & MemRWE[0]
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assign AMOStallD = &MemRWE & MemRWD[1]; // Read after atomic operation causes structural hazard
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assign CMOStallD = (|CMOpE) & (|CMOpD); // *** CMO op after CMO op causes structural hazard.
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assign StoreStallD = MemRWD[1] & MemRWE[0];
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// CMO.inval, CMO.flush, and CMO.clean only update valid and dirty cache bits and never the tag or data arrays. There is no structual hazard.
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// CMO.zero always updates the tag and data arrays, but the cachefsm inserts the wait state if the next instruction reads the tag or data arrays.
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// Structural hazard causes stall if any of these events occur
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assign StructuralStallD = LoadStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | AMOStallD | CMOStallD;
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assign StructuralStallD = LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | AMOStallD | CMOStallD;
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endmodule
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@ -28,17 +28,15 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module dtim import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic FlushW,
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input logic ce, // Chip Enable. 0: Holds ReadDataWordM
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input logic [1:0] MemRWM, // Read/Write control
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input logic [1:0] MemRWE, // Read/Write control
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input logic [P.PA_BITS-1:0] DTIMAdr, // No stall: Execution stage memory address. Stall: Memory stage memory address
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input logic [P.LLEN-1:0] WriteDataM, // Write data from IEU
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input logic [P.LLEN/8-1:0] ByteMaskM, // Selects which bytes within a word to write
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output logic [P.LLEN-1:0] ReadDataWordM, // Read data before subword selection
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output logic DTIMStall,
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output logic DTIMSelWrite
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input logic clk, reset,
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input logic FlushW,
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input logic ce, // Chip Enable. 0: Holds ReadDataWordM
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input logic [1:0] MemRWM, // Read/Write control
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input logic [1:0] MemRWE, // Read/Write control
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input logic [P.PA_BITS-1:0] DTIMAdr, // No stall: Execution stage memory address. Stall: Memory stage memory address
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input logic [P.LLEN-1:0] WriteDataM, // Write data from IEU
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input logic [P.LLEN/8-1:0] ByteMaskM, // Selects which bytes within a word to write
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output logic [P.LLEN-1:0] ReadDataWordM // Read data before subword selection
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);
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logic we;
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@ -50,16 +48,8 @@ module dtim import cvw::*; #(parameter cvw_t P) (
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localparam ADDR_WDITH = $clog2(DEPTH);
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localparam OFFSET = $clog2(LLENBYTES);
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logic DTIMStallHazard, DTIMStallHazardD;
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assign DTIMStallHazard = MemRWM[0] & MemRWE[1];
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flopr #(1) DTIMStallReg(clk, reset, DTIMStallHazard, DTIMStallHazardD);
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assign DTIMStall = DTIMStallHazard & ~DTIMStallHazardD;
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assign DTIMSelWrite = MemRWM[0] & ~(DTIMStallHazard & ~DTIMStall);
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assign we = DTIMSelWrite & ~FlushW; // have to ignore write if Trap.
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assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap.
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ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(DEPTH), .WIDTH(P.LLEN))
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ram(.clk, .ce(ce | DTIMSelWrite), .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
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ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
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endmodule
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@ -150,7 +150,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation
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logic SelDTIM; // Select DTIM rather than bus or D$
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logic [P.XLEN-1:0] WriteDataZM;
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logic DTIMStall;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Pipeline for IEUAdr E to M
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@ -220,7 +219,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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// the trap module.
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assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
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assign GatedStallW = StallW & ~SelHPTW;
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assign CacheBusHPWTStall = DCacheStallM | HPTWStall | BusStall | DTIMStall;
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assign CacheBusHPWTStall = DCacheStallM | HPTWStall | BusStall;
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assign LSUStallM = CacheBusHPWTStall | SpillStallM;
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/////////////////////////////////////////////////////////////////////////////////////////////
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@ -269,10 +268,9 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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if (P.DTIM_SUPPORTED) begin : dtim
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logic [P.PA_BITS-1:0] DTIMAdr;
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logic [1:0] DTIMMemRWM;
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logic DTIMSelWrite;
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// The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
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mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], DTIMSelWrite, DTIMAdr);
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mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], MemRWM[0], DTIMAdr);
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assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0;
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// **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
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// **** create config to support DTIM with floating point.
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@ -280,9 +278,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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dtim #(P) dtim(.clk, .reset, .ce(~GatedStallW), .MemRWE(MemRWE), // *** update when you update the cache RWE
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.MemRWM(DTIMMemRWM),
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.DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM),
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.ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM), .DTIMStall, .DTIMSelWrite);
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end else begin
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assign DTIMStall = '0;
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.ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM));
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end
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if (P.BUS_SUPPORTED) begin : bus
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if(P.DCACHE_SUPPORTED) begin : dcache
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