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https://github.com/openhwgroup/cvw
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fdivsqrt comment improvements
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@ -30,7 +30,7 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
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input logic [P.FMTBITS-1:0] FmtE,
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input logic SqrtE,
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input logic IntDivE,
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input logic [P.DIVBLEN-1:0] IntResultBitsE,
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input logic [P.DIVBLEN-1:0] IntResultBitsE,
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output logic [P.DURLEN-1:0] CyclesE
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);
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@ -28,17 +28,19 @@
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module fdivsqrtexpcalc import cvw::*; #(parameter cvw_t P) (
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input logic [P.FMTBITS-1:0] Fmt,
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input logic [P.NE-1:0] Xe, Ye,
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input logic [P.NE-1:0] Xe, Ye, // input exponents
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input logic Sqrt,
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input logic XZero,
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input logic [P.DIVBLEN-1:0] ell, m,
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output logic [P.NE+1:0] Ue
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input logic [P.DIVBLEN-1:0] ell, m, // number of leading 0s in Xe and Ye
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output logic [P.NE+1:0] Ue // result exponent
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);
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logic [P.NE-2:0] Bias;
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logic [P.NE+1:0] SXExp;
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logic [P.NE+1:0] SExp;
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logic [P.NE+1:0] DExp;
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// Determine exponent bias according to the format
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if (P.FPSIZES == 1) begin
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assign Bias = (P.NE-1)'(P.BIAS);
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@ -28,12 +28,12 @@
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module fdivsqrtfgen2 import cvw::*; #(parameter cvw_t P) (
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input logic up, uz,
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input logic [P.DIVb+3:0] C, U, UM,
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output logic [P.DIVb+3:0] F
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input logic [P.DIVb+3:0] C, U, UM, // Q4.DIVb (extended from shorter forms)
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output logic [P.DIVb+3:0] F // Q4.DIVb
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);
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logic [P.DIVb+3:0] FP, FN, FZ;
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logic [P.DIVb+3:0] FP, FN, FZ; // Q4.DIVb
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// Generate for both positive and negative bits
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// Generate for both positive and negative quotient digits
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assign FP = ~(U << 1) & C;
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assign FN = (UM << 1) | (C & ~(C << 2));
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assign FZ = '0;
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@ -27,14 +27,14 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module fdivsqrtfgen4 import cvw::*; #(parameter cvw_t P) (
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input logic [3:0] udigit,
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input logic [P.DIVb+3:0] C, U, UM,
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output logic [P.DIVb+3:0] F
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input logic [3:0] udigit, // {2, 1, -1, -2}; all cold for zero
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input logic [P.DIVb+3:0] C, U, UM, // Q4.DIVb (extended from shorter forms)
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output logic [P.DIVb+3:0] F // Q4.DIVb
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);
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logic [P.DIVb+3:0] F2, F1, F0, FN1, FN2;
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logic [P.DIVb+3:0] F2, F1, F0, FN1, FN2; // Q4.DIVb
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// Generate for both positive and negative bits
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assign F2 = (~U << 2) & (C << 2);
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// Generate for both positive and negative digits
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assign F2 = (~U << 2) & (C << 2); //
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assign F1 = ~(U << 1) & C;
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assign F0 = '0;
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assign FN1 = (UM << 1) | (C & ~(C << 3));
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@ -57,7 +57,7 @@ module fdivsqrtfsm import cvw::*; #(parameter cvw_t P) (
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// terminate immediately on special cases
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assign FSpecialCaseE = XZeroE | XInfE | XNaNE | (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE;
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if (P.IDIV_ON_FPU) assign SpecialCaseE = IntDivE ? ISpecialCaseE : FSpecialCaseE;
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else assign SpecialCaseE = FSpecialCaseE;
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else assign SpecialCaseE = FSpecialCaseE;
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flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
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always_ff @(posedge clk) begin
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@ -104,14 +104,14 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
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for(i=0; $unsigned(i)<P.DIVCOPIES; i++) begin : iterations
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if (P.RADIX == 2) begin: stage
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fdivsqrtstage2 #(P) fdivsqrtstage(.D, .DBar, .SqrtE,
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.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
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.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
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.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
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.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
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end else begin: stage
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logic j1;
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assign j1 = (i == 0 & ~C[0][P.DIVb-1]);
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fdivsqrtstage4 #(P) fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1,
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.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
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.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
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.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
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.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
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end
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assign WS[i+1] = WSNext[i];
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assign WC[i+1] = WCNext[i];
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@ -29,17 +29,18 @@
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module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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input logic clk,
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input logic IFDivStartE,
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input logic [P.NF:0] Xm, Ym,
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input logic [P.NE-1:0] Xe, Ye,
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input logic [P.NF:0] Xm, Ym, // Floating-point significands
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input logic [P.NE-1:0] Xe, Ye, // Floating-point exponents
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input logic [P.FMTBITS-1:0] FmtE,
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input logic SqrtE,
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input logic XZeroE,
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input logic [2:0] Funct3E,
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output logic [P.NE+1:0] UeM,
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output logic [P.DIVb+3:0] X, D,
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output logic [P.NE+1:0] UeM, // biased exponent of result
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output logic [P.DIVb+3:0] X, D, // Q4.DIVb
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// Int-specific
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input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // U(XLEN.0) inputs from IEU
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input logic IntDivE, W64E,
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// Outputs
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output logic ISpecialCaseE,
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output logic [P.DURLEN-1:0] CyclesE,
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output logic [P.DIVBLEN-1:0] IntNormShiftM,
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@ -18,7 +18,7 @@
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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// httWS://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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@ -27,27 +27,18 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module fdivsqrtqsel2 (
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input logic [3:0] ps, pc,
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input logic [3:0] WS, WC,
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output logic up, uz, un
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);
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logic [3:0] p, g;
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logic magnitude, sign;
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// The quotient selection logic is presented for simplicity, not
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// for efficiency. You can probably optimize your logic to
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// select the proper divisor with less delay.
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// Quotient equations from EE371 lecture notes 13-20
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assign p = ps ^ pc;
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assign g = ps & pc;
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assign magnitude = ~((ps[2]^pc[2]) & (ps[1]^pc[1]) &
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(ps[0]^pc[0]));
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assign sign = (ps[3]^pc[3])^
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(ps[2] & pc[2] | ((ps[2]^pc[2]) &
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(ps[1]&pc[1] | ((ps[1]^pc[1]) &
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(ps[0]&pc[0])))));
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assign magnitude = ~((WS[2]^WC[2]) & (WS[1]^WC[1]) &
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(WS[0]^WC[0]));
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assign sign = (WS[3]^WC[3])^
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(WS[2] & WC[2] | ((WS[2]^WC[2]) &
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(WS[1]&WC[1] | ((WS[1]^WC[1]) &
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(WS[0]&WC[0])))));
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// Produce digit = +1, 0, or -1
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assign up = magnitude & ~sign;
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@ -33,8 +33,8 @@ module fdivsqrtstage2 import cvw::*; #(parameter cvw_t P) (
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input logic [P.DIVb:0] U, UM, // U1.DIVb
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input logic [P.DIVb+3:0] WS, WC, // Q4.DIVb
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input logic [P.DIVb+1:0] C, // Q2.DIVb
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input logic SqrtE,
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output logic un,
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input logic SqrtE,
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output logic un,
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output logic [P.DIVb+1:0] CNext, // Q2.DIVb
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output logic [P.DIVb:0] UNext, UMNext, // U1.DIVb
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output logic [P.DIVb+3:0] WSNext, WCNext // Q4.DIVb
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@ -42,19 +42,13 @@ module fdivsqrtstage2 import cvw::*; #(parameter cvw_t P) (
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/* verilator lint_on UNOPTFLAT */
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logic [P.DIVb+3:0] Dsel; // Q4.DIVb
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logic up, uz;
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logic up, uz;
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logic [P.DIVb+3:0] F; // Q4.DIVb
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logic [P.DIVb+3:0] AddIn; // Q4.DIVb
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logic [P.DIVb+3:0] WSA, WCA; // Q4.DIVb
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// Qmient Selection logic
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// Quotient Selection logic
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// Given partial remainder, select digit of +1, 0, or -1 (up, uz, un)
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// q encoding:
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// 1000 = +2
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// 0100 = +1
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// 0000 = 0
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// 0010 = -1
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// 0001 = -2
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fdivsqrtqsel2 qsel2(WS[P.DIVb+3:P.DIVb], WC[P.DIVb+3:P.DIVb], up, uz, un);
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// Sqrt F generation. Extend C, U, UM to Q4.k
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@ -66,7 +60,7 @@ module fdivsqrtstage2 import cvw::*; #(parameter cvw_t P) (
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else if (uz) Dsel = '0;
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else Dsel = D; // un
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// Partial Product Generation
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// Residual Generation
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// WSA, WCA = WS + WC - qD
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mux2 #(P.DIVb+4) addinmux(Dsel, F, SqrtE, AddIn);
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csa #(P.DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA);
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