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More cleanup.
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parent
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10
src/cache/cachefsm.sv
vendored
10
src/cache/cachefsm.sv
vendored
@ -171,13 +171,9 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
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(CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set.
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// Flush and eviction controls
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(P.ZICBOM_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2]) & CacheBusAck);
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assign SelWay = (CurrState == STATE_WRITEBACK & ~CacheBusAck & ~(CMOp[1] | CMOp[2])) |
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(CurrState == STATE_READY & AnyMiss & LineDirty) |
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(CurrState == STATE_WRITE_LINE) |
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// This is almost the same as setvalid, but on cachehit we don't want to select
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// the nonhit way, but instead want to force this to zero
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(P.ZICBOZ_SUPPORTED & CurrState == STATE_READY & CMOZeroNoEviction & ~CacheHit) |
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(P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CacheBusAck & CMOp[3]);
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assign SelWay = (CurrState == STATE_WRITEBACK & ((~CacheBusAck & ~(CMOp[1] | CMOp[2])) | (P.ZICBOZ_SUPPORTED & CacheBusAck & CMOp[3]))) |
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(CurrState == STATE_READY & ((AnyMiss & LineDirty) | (P.ZICBOZ_SUPPORTED & CMOZeroNoEviction & ~CacheHit))) |
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(CurrState == STATE_WRITE_LINE);
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assign ZeroCacheLine = P.ZICBOZ_SUPPORTED & ((CurrState == STATE_READY & CMOZeroNoEviction) |
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(CurrState == STATE_WRITEBACK & (CMOp[3] & CacheBusAck)));
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assign SelWriteback = (CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2] | ~CacheBusAck)) |
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