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Improved comments about memory read paths

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This commit is contained in:
David Harris 2023-11-01 07:00:17 -07:00
parent dccd7bf5ee
commit 31d9ec08cb
2 changed files with 4 additions and 4 deletions
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4
src/generic/mem/ram1p1rwbe.sv
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@ -90,12 +90,12 @@ module ram1p1rwbe import cvw::*; #(parameter cvw_t P, parameter DEPTH=64, WIDTH=
end
end
// Read
// Combinational read: register address and read after clock edge
logic [$clog2(DEPTH)-1:0] addrd;
flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
assign dout = RAM[addrd];
/* // Read
/* // Alternate read logic reads the old contents of mem[addr]. Increases setup time and adds dout reg, but reduces clk to q
always_ff @(posedge clk)
if(ce) dout <= #1 mem[addr]; */

4
src/generic/mem/ram1p1rwe.sv
View File

@ -71,12 +71,12 @@ module ram1p1rwe import cvw::* ; #(parameter cvw_t P,
// The version with byte write enables it correctly infers block ram.
integer i;
// Read
// Combinational read: register address and read after clock edge
logic [$clog2(DEPTH)-1:0] addrd;
flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
assign dout = RAM[addrd];
/* // Read
/* // Alternate read logic reads the old contents of mem[addr]. Increases setup time and adds dout reg, but reduces clk to q
always_ff @(posedge clk)
if(ce) dout <= #1 mem[addr]; */