mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 10:15:19 +00:00
Merge pull request #533 from ross144/main
Finally fixed the store delay hazard bug.
This commit is contained in:
David Harris
GitHub
commit
bbdcfe24ca
@ -7,6 +7,3 @@ lsu/lsu.sv: logic PAdrM
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lsu/lsu.sv: logic ReadDataM
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lsu/lsu.sv: logic WriteDataM
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lsu/lsu.sv: logic MemRWM
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mmu/hptw.sv: logic SATP_REGW
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privileged/csr.sv: logic MENVCFG_REGW
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privileged/csr.sv: logic SENVCFG_REGW
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File diff suppressed because one or more lines are too long
@ -6,17 +6,17 @@ dst := IP
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#export board := vcu118
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# vcu108
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export XILINX_PART := xcvu095-ffva2104-2-e
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export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
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export board := vcu108
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#export XILINX_PART := xcvu095-ffva2104-2-e
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#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
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#export board := vcu108
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# Arty A7
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# export XILINX_PART := xc7a100tcsg324-1
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# export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
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# export board := ArtyA7
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export XILINX_PART := xc7a100tcsg324-1
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export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
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export board := ArtyA7
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# for Arty A7 and S7 boards
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all: FPGA_VCU
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all: FPGA_Arty
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# VCU 108 and VCU 118 boards
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#all: FPGA_VCU
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@ -54,7 +54,7 @@ PreProcessFiles:
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cp ../../config/rv64gc/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
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./insert_debug_comment.sh
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# modify config *** RT: eventually setup for variably defined sized memory
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sed -i "s/ZICCLSM_SUPPORTED.*/ZICCLSM_SUPPORTED = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/ZICCLSM_SUPPORTED.*/ZICCLSM_SUPPORTED = 1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/RESET_VECTOR.*/RESET_VECTOR = 64'h0000000000001000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/BOOTROM_PRELOAD.*/BOOTROM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/UNCORE_RAM_BASE.*/UNCORE_RAM_BASE = 64'h00002000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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@ -14,10 +14,10 @@ if {$boardName!="ArtyA7"} {
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# read package first
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read_verilog -sv ../src/CopiedFiles_do_not_add_to_repo/cvw.sv
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read_verilog -sv ../src/wallypipelinedsocwrapper.sv
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#read_verilog -sv ../src/wallypipelinedsocwrapper.sv
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# then read top level
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if {$board=="ArtyA7"} {
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read_verilog {../src/fpgaTopArtyA7.v}
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read_verilog {../src/fpgaTopArtyA7.sv}
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} else {
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read_verilog {../src/fpgaTop.v}
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}
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@ -24,6 +24,10 @@
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "config.vh"
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import cvw::*;
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module fpgaTop
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(input default_100mhz_clk,
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(* mark_debug = "true" *) input resetn,
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@ -58,12 +62,12 @@ module fpgaTop
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);
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wire CPUCLK;
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(* mark_debug = "true" *) wire c0_ddr4_ui_clk_sync_rst;
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(* mark_debug = "true" *) wire bus_struct_reset;
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(* mark_debug = "true" *) wire peripheral_reset;
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(* mark_debug = "true" *) wire interconnect_aresetn;
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(* mark_debug = "true" *) wire peripheral_aresetn;
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(* mark_debug = "true" *) wire mb_reset;
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wire c0_ddr4_ui_clk_sync_rst;
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wire bus_struct_reset;
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wire peripheral_reset;
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wire interconnect_aresetn;
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wire peripheral_aresetn;
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wire mb_reset;
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wire HCLKOpen;
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wire HRESETnOpen;
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@ -171,48 +175,48 @@ module fpgaTop
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// Crossbar to Bus ------------------------------------------------
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(* mark_debug = "true" *)wire s00_axi_aclk;
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(* mark_debug = "true" *)wire s00_axi_aresetn;
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(* mark_debug = "true" *)wire [3:0] s00_axi_awid;
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(* mark_debug = "true" *)wire [31:0]s00_axi_awaddr;
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(* mark_debug = "true" *)wire [7:0]s00_axi_awlen;
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(* mark_debug = "true" *)wire [2:0]s00_axi_awsize;
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(* mark_debug = "true" *)wire [1:0]s00_axi_awburst;
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(* mark_debug = "true" *)wire [0:0]s00_axi_awlock;
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(* mark_debug = "true" *)wire [3:0]s00_axi_awcache;
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(* mark_debug = "true" *)wire [2:0]s00_axi_awprot;
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(* mark_debug = "true" *)wire [3:0]s00_axi_awregion;
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(* mark_debug = "true" *)wire [3:0]s00_axi_awqos;
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(* mark_debug = "true" *) wire s00_axi_awvalid;
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(* mark_debug = "true" *) wire s00_axi_awready;
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(* mark_debug = "true" *)wire [63:0]s00_axi_wdata;
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(* mark_debug = "true" *)wire [7:0]s00_axi_wstrb;
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(* mark_debug = "true" *)wire s00_axi_wlast;
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(* mark_debug = "true" *)wire s00_axi_wvalid;
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(* mark_debug = "true" *)wire s00_axi_wready;
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(* mark_debug = "true" *)wire [1:0]s00_axi_bresp;
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(* mark_debug = "true" *)wire s00_axi_bvalid;
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(* mark_debug = "true" *)wire s00_axi_bready;
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wire s00_axi_aclk;
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wire s00_axi_aresetn;
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wire [3:0] s00_axi_awid;
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wire [31:0]s00_axi_awaddr;
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wire [7:0]s00_axi_awlen;
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wire [2:0]s00_axi_awsize;
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wire [1:0]s00_axi_awburst;
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wire [0:0]s00_axi_awlock;
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wire [3:0]s00_axi_awcache;
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wire [2:0]s00_axi_awprot;
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wire [3:0]s00_axi_awregion;
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wire [3:0]s00_axi_awqos;
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wire s00_axi_awvalid;
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wire s00_axi_awready;
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wire [63:0]s00_axi_wdata;
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wire [7:0]s00_axi_wstrb;
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wire s00_axi_wlast;
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wire s00_axi_wvalid;
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wire s00_axi_wready;
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wire [1:0]s00_axi_bresp;
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wire s00_axi_bvalid;
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wire s00_axi_bready;
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wire [3:0] s00_axi_arid;
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(* mark_debug = "true" *)wire [31:0]s00_axi_araddr;
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(* mark_debug = "true" *)wire [7:0]s00_axi_arlen;
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(* mark_debug = "true" *)wire [2:0]s00_axi_arsize;
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(* mark_debug = "true" *)wire [1:0]s00_axi_arburst;
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(* mark_debug = "true" *)wire [0:0]s00_axi_arlock;
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(* mark_debug = "true" *)wire [3:0]s00_axi_arcache;
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(* mark_debug = "true" *)wire [2:0]s00_axi_arprot;
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(* mark_debug = "true" *)wire [3:0]s00_axi_arregion;
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(* mark_debug = "true" *)wire [3:0]s00_axi_arqos;
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(* mark_debug = "true" *)wire s00_axi_arvalid;
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(* mark_debug = "true" *)wire s00_axi_arready;
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(* mark_debug = "true" *)wire [63:0]s00_axi_rdata;
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(* mark_debug = "true" *)wire [1:0]s00_axi_rresp;
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(* mark_debug = "true" *)wire s00_axi_rlast;
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(* mark_debug = "true" *)wire s00_axi_rvalid;
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(* mark_debug = "true" *)wire s00_axi_rready;
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wire [31:0]s00_axi_araddr;
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wire [7:0]s00_axi_arlen;
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wire [2:0]s00_axi_arsize;
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wire [1:0]s00_axi_arburst;
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wire [0:0]s00_axi_arlock;
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wire [3:0]s00_axi_arcache;
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wire [2:0]s00_axi_arprot;
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wire [3:0]s00_axi_arregion;
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wire [3:0]s00_axi_arqos;
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wire s00_axi_arvalid;
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wire s00_axi_arready;
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wire [63:0]s00_axi_rdata;
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wire [1:0]s00_axi_rresp;
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wire s00_axi_rlast;
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wire s00_axi_rvalid;
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wire s00_axi_rready;
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(* mark_debug = "true" *)wire [3:0] s00_axi_bid;
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(* mark_debug = "true" *)wire [3:0] s00_axi_rid;
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wire [3:0] s00_axi_bid;
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wire [3:0] s00_axi_rid;
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// 64to32 dwidth converter input interface-------------------------
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wire s01_axi_aclk;
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@ -227,8 +231,8 @@ module fpgaTop
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wire [2:0]s01_axi_awprot;
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wire [3:0]s01_axi_awregion;
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wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC
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(* mark_debug = "true" *) wire s01_axi_awvalid;
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(* mark_debug = "true" *) wire s01_axi_awready;
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wire s01_axi_awvalid;
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wire s01_axi_awready;
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wire [63:0]s01_axi_wdata;
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wire [7:0]s01_axi_wstrb;
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wire s01_axi_wlast;
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@ -265,8 +269,8 @@ module fpgaTop
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wire [2:0]axi4in_axi_awprot;
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wire [3:0]axi4in_axi_awregion;
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wire [3:0]axi4in_axi_awqos;
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(* mark_debug = "true" *) wire axi4in_axi_awvalid;
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(* mark_debug = "true" *) wire axi4in_axi_awready;
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wire axi4in_axi_awvalid;
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wire axi4in_axi_awready;
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wire [31:0]axi4in_axi_wdata;
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wire [3:0]axi4in_axi_wstrb;
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wire axi4in_axi_wlast;
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@ -293,30 +297,30 @@ module fpgaTop
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wire axi4in_axi_rready;
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// AXI4 to AXI4-Lite Protocol converter output
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(* mark_debug = "true" *) wire [31:0]SDCin_axi_awaddr;
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(* mark_debug = "true" *) wire [2:0]SDCin_axi_awprot;
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(* mark_debug = "true" *) wire SDCin_axi_awvalid;
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(* mark_debug = "true" *) wire SDCin_axi_awready;
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(* mark_debug = "true" *) wire [31:0]SDCin_axi_wdata;
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(* mark_debug = "true" *) wire [3:0]SDCin_axi_wstrb;
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(* mark_debug = "true" *) wire SDCin_axi_wvalid;
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(* mark_debug = "true" *) wire SDCin_axi_wready;
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(* mark_debug = "true" *) wire [1:0]SDCin_axi_bresp;
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(* mark_debug = "true" *) wire SDCin_axi_bvalid;
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(* mark_debug = "true" *) wire SDCin_axi_bready;
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(* mark_debug = "true" *) wire [31:0]SDCin_axi_araddr;
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(* mark_debug = "true" *) wire [2:0]SDCin_axi_arprot;
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(* mark_debug = "true" *) wire SDCin_axi_arvalid;
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(* mark_debug = "true" *) wire SDCin_axi_arready;
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(* mark_debug = "true" *) wire [31:0]SDCin_axi_rdata;
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(* mark_debug = "true" *) wire [1:0]SDCin_axi_rresp;
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(* mark_debug = "true" *) wire SDCin_axi_rvalid;
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(* mark_debug = "true" *) wire SDCin_axi_rready;
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wire [31:0]SDCin_axi_awaddr;
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wire [2:0]SDCin_axi_awprot;
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wire SDCin_axi_awvalid;
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wire SDCin_axi_awready;
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wire [31:0]SDCin_axi_wdata;
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wire [3:0]SDCin_axi_wstrb;
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wire SDCin_axi_wvalid;
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wire SDCin_axi_wready;
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wire [1:0]SDCin_axi_bresp;
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wire SDCin_axi_bvalid;
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wire SDCin_axi_bready;
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wire [31:0]SDCin_axi_araddr;
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wire [2:0]SDCin_axi_arprot;
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wire SDCin_axi_arvalid;
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wire SDCin_axi_arready;
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wire [31:0]SDCin_axi_rdata;
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wire [1:0]SDCin_axi_rresp;
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wire SDCin_axi_rvalid;
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wire SDCin_axi_rready;
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// ----------------------------------------------------------------
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// 32to64 dwidth converter input interface -----------------------
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(* mark_debug = "true" *) wire [31:0]SDCout_axi_awaddr;
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(* mark_debug = "true" *) wire [7:0]SDCout_axi_awlen;
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wire [31:0]SDCout_axi_awaddr;
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wire [7:0]SDCout_axi_awlen;
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wire [2:0]SDCout_axi_awsize;
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wire [1:0]SDCout_axi_awburst;
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wire [0:0]SDCout_axi_awlock;
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@ -324,16 +328,16 @@ module fpgaTop
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wire [2:0]SDCout_axi_awprot;
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wire [3:0]SDCout_axi_awregion;
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wire [3:0]SDCout_axi_awqos;
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(* mark_debug = "true" *) wire SDCout_axi_awvalid;
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(* mark_debug = "true" *) wire SDCout_axi_awready;
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(* mark_debug = "true" *) wire [31:0]SDCout_axi_wdata;
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wire SDCout_axi_awvalid;
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wire SDCout_axi_awready;
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wire [31:0]SDCout_axi_wdata;
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wire [3:0]SDCout_axi_wstrb;
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(* mark_debug = "true" *) wire SDCout_axi_wlast;
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(* mark_debug = "true" *) wire SDCout_axi_wvalid;
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(* mark_debug = "true" *)wire SDCout_axi_wready;
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(* mark_debug = "true" *) wire [1:0]SDCout_axi_bresp;
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(* mark_debug = "true" *) wire SDCout_axi_bvalid;
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(* mark_debug = "true" *) wire SDCout_axi_bready;
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wire SDCout_axi_wlast;
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wire SDCout_axi_wvalid;
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wire SDCout_axi_wready;
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wire [1:0]SDCout_axi_bresp;
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wire SDCout_axi_bvalid;
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wire SDCout_axi_bready;
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wire [31:0]SDCout_axi_araddr;
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wire [7:0]SDCout_axi_arlen;
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wire [2:0]SDCout_axi_arsize;
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@ -352,45 +356,45 @@ module fpgaTop
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wire SDCout_axi_rready;
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// Output Interface
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(* mark_debug = "true" *) wire [3:0]m01_axi_awid;
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(* mark_debug = "true" *) wire [31:0]m01_axi_awaddr;
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(* mark_debug = "true" *) wire [7:0]m01_axi_awlen;
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(* mark_debug = "true" *) wire [2:0]m01_axi_awsize;
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(* mark_debug = "true" *) wire [1:0]m01_axi_awburst;
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(* mark_debug = "true" *) wire [0:0]m01_axi_awlock;
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(* mark_debug = "true" *) wire [3:0]m01_axi_awcache;
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(* mark_debug = "true" *) wire [2:0]m01_axi_awprot;
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(* mark_debug = "true" *) wire [3:0]m01_axi_awregion;
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(* mark_debug = "true" *) wire [3:0]m01_axi_awqos;
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(* mark_debug = "true" *) wire m01_axi_awvalid;
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(* mark_debug = "true" *) wire m01_axi_awready;
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(* mark_debug = "true" *) wire [63:0]m01_axi_wdata;
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(* mark_debug = "true" *) wire [7:0]m01_axi_wstrb;
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(* mark_debug = "true" *) wire m01_axi_wlast;
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(* mark_debug = "true" *) wire m01_axi_wvalid;
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(* mark_debug = "true" *) wire m01_axi_wready;
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(* mark_debug = "true" *) wire [3:0] m01_axi_bid;
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(* mark_debug = "true" *) wire [1:0]m01_axi_bresp;
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(* mark_debug = "true" *) wire m01_axi_bvalid;
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(* mark_debug = "true" *) wire m01_axi_bready;
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(* mark_debug = "true" *) wire [3:0] m01_axi_arid;
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(* mark_debug = "true" *) wire [31:0]m01_axi_araddr;
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(* mark_debug = "true" *) wire [7:0]m01_axi_arlen;
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(* mark_debug = "true" *) wire [2:0]m01_axi_arsize;
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(* mark_debug = "true" *) wire [1:0]m01_axi_arburst;
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(* mark_debug = "true" *) wire [0:0]m01_axi_arlock;
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(* mark_debug = "true" *) wire [3:0]m01_axi_arcache;
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(* mark_debug = "true" *) wire [2:0]m01_axi_arprot;
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(* mark_debug = "true" *) wire [3:0]m01_axi_arregion;
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(* mark_debug = "true" *) wire [3:0]m01_axi_arqos;
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(* mark_debug = "true" *) wire m01_axi_arvalid;
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(* mark_debug = "true" *) wire m01_axi_arready;
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(* mark_debug = "true" *) wire [3:0] m01_axi_rid;
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(* mark_debug = "true" *) wire [63:0]m01_axi_rdata;
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(* mark_debug = "true" *) wire [1:0]m01_axi_rresp;
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(* mark_debug = "true" *) wire m01_axi_rlast;
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(* mark_debug = "true" *) wire m01_axi_rvalid;
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(* mark_debug = "true" *) wire m01_axi_rready;
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wire [3:0]m01_axi_awid;
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wire [31:0]m01_axi_awaddr;
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wire [7:0]m01_axi_awlen;
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wire [2:0]m01_axi_awsize;
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wire [1:0]m01_axi_awburst;
|
||||
wire [0:0]m01_axi_awlock;
|
||||
wire [3:0]m01_axi_awcache;
|
||||
wire [2:0]m01_axi_awprot;
|
||||
wire [3:0]m01_axi_awregion;
|
||||
wire [3:0]m01_axi_awqos;
|
||||
wire m01_axi_awvalid;
|
||||
wire m01_axi_awready;
|
||||
wire [63:0]m01_axi_wdata;
|
||||
wire [7:0]m01_axi_wstrb;
|
||||
wire m01_axi_wlast;
|
||||
wire m01_axi_wvalid;
|
||||
wire m01_axi_wready;
|
||||
wire [3:0] m01_axi_bid;
|
||||
wire [1:0]m01_axi_bresp;
|
||||
wire m01_axi_bvalid;
|
||||
wire m01_axi_bready;
|
||||
wire [3:0] m01_axi_arid;
|
||||
wire [31:0]m01_axi_araddr;
|
||||
wire [7:0]m01_axi_arlen;
|
||||
wire [2:0]m01_axi_arsize;
|
||||
wire [1:0]m01_axi_arburst;
|
||||
wire [0:0]m01_axi_arlock;
|
||||
wire [3:0]m01_axi_arcache;
|
||||
wire [2:0]m01_axi_arprot;
|
||||
wire [3:0]m01_axi_arregion;
|
||||
wire [3:0]m01_axi_arqos;
|
||||
wire m01_axi_arvalid;
|
||||
wire m01_axi_arready;
|
||||
wire [3:0] m01_axi_rid;
|
||||
wire [63:0]m01_axi_rdata;
|
||||
wire [1:0]m01_axi_rresp;
|
||||
wire m01_axi_rlast;
|
||||
wire m01_axi_rvalid;
|
||||
wire m01_axi_rready;
|
||||
|
||||
// Old SDC input
|
||||
// wire [3:0] SDCDatIn;
|
||||
@ -401,7 +405,7 @@ module fpgaTop
|
||||
wire sd_cmd_reg_t;
|
||||
|
||||
// SD Card Interrupt signal
|
||||
(* mark_debug = "true" *) wire SDCIntr;
|
||||
wire SDCIntr;
|
||||
|
||||
// New SDC Data IOBUF connections
|
||||
wire [3:0] sd_dat_i;
|
||||
@ -409,10 +413,10 @@ module fpgaTop
|
||||
wire sd_dat_reg_t;
|
||||
|
||||
|
||||
(* mark_debug = "true" *) wire c0_init_calib_complete;
|
||||
wire c0_init_calib_complete;
|
||||
wire dbg_clk;
|
||||
wire [511 : 0] dbg_bus;
|
||||
(* mark_debug = "true" *) wire ui_clk_sync_rst;
|
||||
wire ui_clk_sync_rst;
|
||||
|
||||
wire CLK208;
|
||||
wire clk167;
|
||||
@ -421,9 +425,9 @@ module fpgaTop
|
||||
wire app_sr_active;
|
||||
wire app_ref_ack;
|
||||
wire app_zq_ack;
|
||||
(* mark_debug = "true" *) wire mmcm_locked;
|
||||
wire mmcm_locked;
|
||||
wire [11:0] device_temp;
|
||||
(* mark_debug = "true" *) wire mmcm1_locked;
|
||||
wire mmcm1_locked;
|
||||
|
||||
|
||||
assign GPIOIN = {28'b0, GPI};
|
||||
@ -470,7 +474,7 @@ module fpgaTop
|
||||
// reset controller XILINX IP
|
||||
xlnx_proc_sys_reset xlnx_proc_sys_reset_0
|
||||
(.slowest_sync_clk(CPUCLK),
|
||||
.ext_reset_in(c0_ddr4_ui_clk_sync_rst),
|
||||
.ext_reset_in(1'b0),
|
||||
.aux_reset_in(south_reset),
|
||||
.mb_debug_sys_rst(1'b0),
|
||||
.dcm_locked(c0_init_calib_complete),
|
||||
@ -482,47 +486,18 @@ module fpgaTop
|
||||
|
||||
// wally
|
||||
// *** FIXME add sdc interrupt and HSELEXTSDC, remove old sdc
|
||||
wallypipelinedsocwrapper wallypipelinedsocwrapper
|
||||
(.clk(CPUCLK),
|
||||
.reset_ext(bus_struct_reset),
|
||||
.reset(),
|
||||
// bus interface
|
||||
.HRDATAEXT(HRDATAEXT),
|
||||
.HREADYEXT(HREADYEXT),
|
||||
.HRESPEXT(HRESPEXT),
|
||||
.HSELEXT(HSELEXT),
|
||||
.HSELEXTSDC(HSELEXTSDC),
|
||||
.HCLK(HCLKOpen), // open
|
||||
.HRESETn(HRESETnOpen), // open
|
||||
.HADDR(HADDR),
|
||||
.HWDATA(HWDATA),
|
||||
.HWSTRB(HWSTRB),
|
||||
.HWRITE(HWRITE),
|
||||
.HSIZE(HSIZE),
|
||||
.HBURST(HBURST),
|
||||
.HPROT(HPROT),
|
||||
.HTRANS(HTRANS),
|
||||
.HMASTLOCK(HMASTLOCK),
|
||||
.HREADY(HREADY),
|
||||
// MTIME
|
||||
.TIMECLK(1'b0),
|
||||
// GPIO
|
||||
.GPIOIN(GPIOIN),
|
||||
.GPIOOUT(GPIOOUT),
|
||||
.GPIOEN(GPIOEN),
|
||||
// UART
|
||||
.UARTSin(UARTSin),
|
||||
.UARTSout(UARTSout),
|
||||
.SDCIntr(SDCIntr)
|
||||
// SD Card
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
.SDCDatIn(SDCDat),
|
||||
.SDCCmdIn(SDCCmdIn),
|
||||
.SDCCmdOut(SDCCmdOut),
|
||||
.SDCCmdOE(SDCCmdOE),
|
||||
.SDCCLK(SDCCLK));
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
);
|
||||
|
||||
`include "parameter-defs.vh"
|
||||
|
||||
wallypipelinedsoc #(P)
|
||||
wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(),
|
||||
.HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT,
|
||||
.HSELEXTSDC, .HCLK(HCLKOpen), .HRESETn(HRESETnOpen),
|
||||
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0),
|
||||
.GPIOIN, .GPIOOUT, .GPIOEN,
|
||||
.UARTSin, .UARTSout, .SDCIntr);
|
||||
|
||||
|
||||
// ahb lite to axi bridge
|
||||
xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0
|
||||
@ -431,6 +431,6 @@ module controller import cvw::*; #(parameter cvw_t P) (
|
||||
// *** RT: Check that atomic after atomic works correctly.
|
||||
//assign StoreStallD = ((|CMOpE)) & ((|CMOpD));
|
||||
logic AMOHazard;
|
||||
assign AMOHazard = &MemRWM & MemRWE[1];
|
||||
assign AMOHazard = &MemRWE & MemRWD[1];
|
||||
assign StoreStallD = ((|CMOpE) & (|CMOpD)) | AMOHazard;
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user