Rose Thompson 747f453bb5 Passes lint with some exceptions. Still need to add misaligned store support.		2023-10-27 14:41:42 -05:00
..
cache	Modified log2 coding to avoid synthesis warning	2023-10-19 11:16:02 -07:00
ebu	Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now.	2023-07-21 16:31:26 -05:00
fpu	Renamed wally-config to config in many comments	2023-10-16 13:49:09 -07:00
generic	Merge branch 'boot' into mergeBoot	2023-07-21 17:43:45 -05:00
hazard	Cleaned up the implementation changes for wfi.	2023-10-24 23:11:48 -05:00
ieu	minfo test working again with mconfigptr for RV64	2023-10-15 06:41:52 -07:00
ifu	Added support for branch counters when there is no branch predictor.	2023-10-23 15:32:03 -05:00
lsu	Passes lint with some exceptions. Still need to add misaligned store support.	2023-10-27 14:41:42 -05:00
mdu	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-06-15 15:38:38 -05:00
mmu	UpdateDA cleanup: don't assert UpdateDA when there is no SVADU	2023-10-04 09:57:13 -07:00
privileged	Cleaned up the implementation changes for wfi.	2023-10-24 23:11:48 -05:00
uncore	Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates	2023-10-18 05:50:41 -07:00
wally	The misaligned load alignment lints.	2023-10-27 11:41:49 -05:00
cvw.sv	Addec ZICCLSM to config files and started on lsu instance.	2023-10-27 13:07:23 -05:00