Merge pull request #537 from ross144/main

Almost having working Verilator.  One issue in the testbench remains.

config/buildroot/config.vh

@@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/rv32e/config.vh

@@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/rv32gc/config.vh

@@ -71,6 +71,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/rv32i/config.vh

@@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/rv32imc/config.vh

@@ -69,6 +69,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/rv64fpquad/config.vh

@@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/rv64gc/config.vh

@@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/rv64i/config.vh

@@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/shared/parameter-defs.vh

@@ -38,6 +38,7 @@ localparam cvw_t P = '{
   ICACHE_NUMWAYS :        ICACHE_NUMWAYS,
   ICACHE_WAYSIZEINBYTES :        ICACHE_WAYSIZEINBYTES,
   ICACHE_LINELENINBITS :        ICACHE_LINELENINBITS,
+  CACHE_SRAMLEN : CACHE_SRAMLEN,
   IDIV_BITSPERCYCLE :        IDIV_BITSPERCYCLE,
   IDIV_ON_FPU :        IDIV_ON_FPU,
   PMP_ENTRIES :        PMP_ENTRIES,

src/cache/cacheway.sv

@@ -129,21 +129,20 @@ module cacheway import cvw::*; #(parameter cvw_t P,
 
   genvar               words;
 
-  localparam           SRAMLEN = 128;             // *** make this a global parameter
-  localparam           NUMSRAM = LINELEN/SRAMLEN;
-  localparam           SRAMLENINBYTES = SRAMLEN/8;
+  localparam           NUMSRAM = LINELEN/P.CACHE_SRAMLEN;
+  localparam           SRAMLENINBYTES = P.CACHE_SRAMLEN/8;
   localparam           LOGNUMSRAM = $clog2(NUMSRAM);
   
   for(words = 0; words < NUMSRAM; words++) begin: word
     if (!READ_ONLY_CACHE) begin:wordram
-      ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
-      .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
-      .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
+      ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
+      .dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
+      .din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
       .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
     end else begin:wordram // no byte-enable needed for i$.
-      ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
-      .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
-      .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
+      ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
+      .dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
+      .din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
       .we(SelectedWriteWordEn));
     end
   end

src/cvw.sv

@@ -80,6 +80,7 @@ typedef struct packed {
   int           ICACHE_NUMWAYS;
   int           ICACHE_WAYSIZEINBYTES;
   int           ICACHE_LINELENINBITS;
+  int           CACHE_SRAMLEN;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

src/generic/mem/ram2p1r1wbe.sv

@@ -110,11 +110,11 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
     // ***************************************************************************
     integer i;
     
-  /*  initial begin // initialize memory for simulation only; not needed because done in the testbench now
+    initial begin // initialize memory for simulation only; not needed because done in the testbench now
       integer j;
       for (j=0; j < DEPTH; j++) 
         mem[j] = '0;
-    end */
+    end 
     
     // Read
     logic [$clog2(DEPTH)-1:0] ra1d;

testbench/common/DCacheFlushFSM.sv

@@ -43,8 +43,8 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P)
     localparam numways        = P.DCACHE_NUMWAYS;
     localparam linelen        = P.DCACHE_LINELENINBITS;
     localparam linebytelen    = linelen/8;
-    localparam sramlen        = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;            
-    localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
+    localparam sramlen        = P.CACHE_SRAMLEN;
+    localparam cachesramwords = linelen/sramlen;
     localparam numwords       = sramlen/P.XLEN;
     localparam lognumlines    = $clog2(numlines);
     localparam loglinebytelen = $clog2(linebytelen);
@@ -97,7 +97,10 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P)
                   // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
                   // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
                   //ShadowRAM[CacheAdr[j][i][k] >> $clog2(P.XLEN/8)] = cacheline[P.XLEN*(k+1)-1:P.XLEN*k];
-                  ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + k] = CacheData[j][i][l][P.XLEN*k +: P.XLEN];
+                  /* verilator lint_off WIDTHTRUNC */
+                  // *** lint error: address trunc warning for shadowram index
+                  ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + {{{P.PA_BITS-32}{1'b0}}, k}] = CacheData[j][i][l][P.XLEN*k +: P.XLEN];
+                  /* verilator lint_on WIDTHTRUNC */
                 end
               end
             end
@@ -124,16 +127,26 @@ module copyShadow import cvw::*; #(parameter cvw_t P,
    output logic [P.XLEN-1:0]           CacheTag,
    output logic                       CacheValid,
    output logic                       CacheDirty);
+
+  logic [P.XLEN+1:0]               TagExtend;
+  logic [P.XLEN+1:0]               IndexExtend;
+  logic [P.XLEN+1:0]               CacheWordExtend;
+  logic [P.XLEN+1:0]               CacheAdrExtend;
   
+  assign TagExtend = {{{P.XLEN-(P.PA_BITS-tagstart)+2}{1'b0}}, tag};
+  assign IndexExtend = {{{P.XLEN-32+2}{1'b0}}, index};
+  assign CacheWordExtend = {{{P.XLEN-32+2}{1'b0}}, cacheWord};
 
   always_ff @(posedge clk) begin
     if(start) begin
-      CacheTag = tag;
+      CacheTag = TagExtend[P.XLEN-1:0];
       CacheValid = valid;
       CacheDirty = dirty;
       CacheData = data;
-      CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8));
+      CacheAdrExtend = (TagExtend << tagstart) + (IndexExtend << loglinebytelen) + (CacheWordExtend << $clog2(sramlen/8));
     end
   end
+
+  assign CacheAdr = CacheAdrExtend[P.PA_BITS-1:0];
   
 endmodule

testbench/common/functionName.sv

@@ -30,15 +30,15 @@ module FunctionName import cvw::*; #(parameter cvw_t P) (
   input string ProgramLabelMapFile
   );
   
-  logic [P.XLEN-1:0] ProgramAddrMapMemory [];
-  string 	    ProgramLabelMapMemory [integer];
+  logic [P.XLEN-1:0] ProgramAddrMapMemory [logic [P.XLEN-1:0]];
+  string 	    ProgramLabelMapMemory [logic [P.XLEN-1:0]];
   string 	    FunctionName;
   
 
   logic [P.XLEN-1:0] PCF, PCD, PCE, PCM, FunctionAddr, PCM_temp, PCMOld;
   logic 	    StallD, StallE, StallM, FlushD, FlushE, FlushM;
   logic 		InstrValidM;
-  integer 	    ProgramAddrIndex, ProgramAddrIndexQ;
+  logic [P.XLEN-1:0] 	    ProgramAddrIndex, ProgramAddrIndexQ;
 
   assign PCF = testbench.dut.core.ifu.PCF;
   assign StallD = testbench.dut.core.StallD;
@@ -62,7 +62,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) (
   task automatic bin_search_min;
     input logic [P.XLEN-1:0] pc;
     input logic [P.XLEN-1:0] length;
-    ref logic [P.XLEN-1:0]   array [];
+    ref logic [P.XLEN-1:0]   array [logic [P.XLEN-1:0]];
     output logic [P.XLEN-1:0] minval;
     output     logic [P.XLEN-1:0] mid;
 
@@ -109,8 +109,9 @@ module FunctionName import cvw::*; #(parameter cvw_t P) (
   endtask // bin_search_min
 
   integer ProgramAddrMapFP, ProgramLabelMapFP;
-  integer ProgramAddrMapLineCount, ProgramLabelMapLineCount;
-  longint ProgramAddrMapLine;
+  logic [P.XLEN-1:0] ProgramAddrMapLineCount;
+  logic [P.XLEN-1:0] ProgramLabelMapLineCount;
+  logic [P.XLEN-1:0] ProgramAddrMapLine;
   string  ProgramLabelMapLine;
   integer status;
   
@@ -118,22 +119,28 @@ module FunctionName import cvw::*; #(parameter cvw_t P) (
   // preload
 //  initial begin
   always @ (negedge reset) begin
+
+    // cannot readmemh directoy to a dynmaic array. Sad times :(
+    // Let's initialize a static array with FFFF_FFFF for all addresses.
+    // Then we can readmemh and finally copy to the dynamic array.
+    
 	// clear out the old mapping between programs.
     ProgramAddrMapMemory.delete();
     ProgramLabelMapMemory.delete();
 
-    $readmemh(ProgramAddrMapFile, ProgramAddrMapMemory);
+    // Unfortunately verilator version 5.011 readmemh does not support dynamic arrays
+    //$readmemh(ProgramAddrMapFile, ProgramAddrMapMemory);
     // we need to count the number of lines in the file so we can set FunctionRadixLineCount.
 
     ProgramAddrMapLineCount = 0;
     ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
 
     // read line by line to count lines
-    if (ProgramAddrMapFP) begin
+    if (ProgramAddrMapFP != '0) begin
       while (! $feof(ProgramAddrMapFP)) begin
-	status = $fscanf(ProgramAddrMapFP, "%h\n", ProgramAddrMapLine);
-	
-	ProgramAddrMapLineCount = ProgramAddrMapLineCount + 1;
+	    status = $fscanf(ProgramAddrMapFP, "%h\n", ProgramAddrMapLine);
+        ProgramAddrMapMemory[ProgramAddrMapLineCount] = ProgramAddrMapLine;
+	    ProgramAddrMapLineCount = ProgramAddrMapLineCount + 1;
       end
     end else begin
       $display("Cannot open file %s for reading.", ProgramAddrMapFile);
@@ -147,7 +154,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) (
     ProgramLabelMapLineCount = 0;
     ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
     
-    if (ProgramLabelMapFP) begin
+    if (ProgramLabelMapFP != '0) begin
       while (! $feof(ProgramLabelMapFP)) begin
 	status = $fscanf(ProgramLabelMapFP, "%s\n", ProgramLabelMapLine);
 	ProgramLabelMapMemory[ProgramLabelMapLineCount] = ProgramLabelMapLine;

testbench/common/ramxdetector.sv

@@ -36,7 +36,9 @@ module ramxdetector #(parameter XLEN, LLEN) (
 );
 
   always_ff @(posedge clk)
+    /* verilator lint_off WIDTHXZEXPAND */
     if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin
+      /* verilator lint_on WIDTHXZEXPAND */
       $display("WARNING: Attempting to read from unitialized RAM.  Processor may go haywire if it uses x value. But this is normal in WALLY-mmu tests.");
       $display("  PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM);
       //$stop;

testbench/common/riscvassertions.sv

@@ -42,7 +42,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
     assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
     assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
     assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
-    assert (P.UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
+    assert (P.UNCORE_RAM_RANGE >= 64'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 64'h07FFFFFF");
 	  assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
     assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported");
     assert (P.U_SUPPORTED || (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");

testbench/testbench.sv

@@ -320,6 +320,7 @@ module testbench;
   ////////////////////////////////////////////////////////////////////////////////
   // Some memories are not reset, but should be zeros or set to some initial value for simulation
   ////////////////////////////////////////////////////////////////////////////////
+/* -----\/----- EXCLUDED -----\/-----
   integer adrindex;
   always @(posedge clk) begin
     if (ResetMem)  // program memory is sometimes reset
@@ -339,13 +340,49 @@ module testbench;
       end
     end
   end
+ -----/\----- EXCLUDED -----/\----- */
 
+  // still not working in this format
+/* -----\/----- EXCLUDED -----\/-----
+  integer adrindex;
+  if (P.UNCORE_RAM_SUPPORTED) begin
+    always @(posedge clk) begin
+      if (ResetMem)  // program memory is sometimes reset
+        for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) 
+          dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
+    end
+  end
+  
+  genvar adrindex2;
+  
+  if (P.BPRED_SUPPORTED & (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)) begin
+    for(adrindex2 = 0; adrindex2 < 2**P.BPRED_NUM_LHR; adrindex2++)
+      always @(posedge clk) begin
+        dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex2] = 0;
+    end
+  end        
+
+  if (P.BPRED_SUPPORTED) begin
+    always @(posedge clk) 
+      dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[0] = 0;    
+    for(adrindex2 = 0; adrindex2 < 2**P.BTB_SIZE; adrindex2++)
+      always @(posedge clk) begin
+        dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex2] = 0;
+      end
+    for(adrindex2 = 0; adrindex2 < 2**P.BPRED_SIZE; adrindex2++)
+      always @(posedge clk) begin
+        dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex2] = 0;
+      end
+  end
+ -----/\----- EXCLUDED -----/\----- */
+  
   ////////////////////////////////////////////////////////////////////////////////
   // load memories with program image
   ////////////////////////////////////////////////////////////////////////////////
-  always @(posedge clk) begin
-    if (LoadMem) begin
-      if (P.SDC_SUPPORTED) begin
+
+  if (P.SDC_SUPPORTED) begin
+    always @(posedge clk) begin
+      if (LoadMem) begin
         string romfilename, sdcfilename;
         romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
         sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
@@ -353,13 +390,29 @@ module testbench;
         //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
         // shorten sdc timers for simulation
         //dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
-      end 
-      else if (P.IROM_SUPPORTED)     $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
-      else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
-      if (P.DTIM_SUPPORTED)     $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
-      $display("Read memfile %s", memfilename);
+      end
     end
-  end  
+  end else if (P.IROM_SUPPORTED) begin
+    always @(posedge clk) begin
+      if (LoadMem) begin
+        $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
+      end
+    end
+  end else if (P.BUS_SUPPORTED) begin
+    always @(posedge clk) begin
+      if (LoadMem) begin
+        $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+      end
+    end
+  end 
+  if (P.DTIM_SUPPORTED) begin
+    always @(posedge clk) begin
+      if (LoadMem) begin
+        $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+        $display("Read memfile %s", memfilename);
+      end
+    end
+  end
  
   ////////////////////////////////////////////////////////////////////////////////
   // Actual hardware
@@ -508,10 +561,15 @@ module testbench;
     testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
     testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
     /* verilator lint_off INFINITELOOP */
+    /* verilator lint_off WIDTHXZEXPAND */
     while (signature[i] !== 'bx) begin
+      /* verilator lint_on WIDTHXZEXPAND */
       logic [P.XLEN-1:0] sig;
+      // **************************************
+      // ***** BUG BUG BUG make sure RT undoes this.
       if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
       else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
+      //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
       //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
       if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin  
         errors = errors+1;